SU575647A1 - Device for obtaining exponential function - Google Patents

Description

(54) DEVICE FOR RECEPTION

INDICATIVE POWER FUNCTION

Nor 5-7 and adder 8 parallel action,

The Raar bottom grid of registers 1 and 2 is divided into two equal groups of high and low bits. In block 3, the address determined by the high bits of register 1 contains the values of the natural logarithm. In block 4, the values determined by most significant bits 1 and 2 are simultaneously recorded in Z. quotient. The lower bits of registers 1 and 2 are connected h: respectively to the first inputs of multiplication blocks 5 and 6, to the second inputs of which the outputs of blocks 3 and 4 are connected, the second output of block 4 is connected to the second input of block 7. The outputs of blocks 5 and b are connected to two inputs of adder 8, the third input of which is structurally fed to one. The output of the adder is connected to the first input of the multiplication unit 7, the output of which is the output of the device

Blocks 5-7 can be implemented according to any scheme, for example, tabular (on a one-way memory). In the latter case, the device speed is maximum.

 The device works as follows

After writing in registers 1 and 2, codes of numbers X and Y, the values of their most significant bits are read from the memorized blocks 3 and 4, respectively, of the natural logarithm of the code defined by the higher bits and two values written

with IYfT

VcT /

At the same address - X,

st

In the second cycle of operation, the obtained values of ls-arithm and quotient are multiplied in blocks 5 and 6 by the code values in the lower bits of registers 1 and 2, respectively. The resulting products are summed in the third cycle with the numeric unit in the adder 8. In the fourth cycle of operation, the code value is multiplied by the result of the summation of the first products. The result of the multiplication is its value of the unknown function x

The speed of the device is determined by the execution time of the multiplication operations in the second and fourth cycles. When blocks 5–7 are implemented on a one-way memory, the multiplication time corresponds to the memory access time and is numerically equal to a few microseconds.

The total time for obtaining an exponential-power function in this case is equal to the interval of four memory accesses. With the implementation of blocks 5–7 by ordinary parallel or sequential multiplication schemes with a small number of bits of one of the factors, the multiplication time increases slightly, and the calculation error of the function is several orders of magnitude less than permissible, since the accuracy required in control and regulation tasks currently exceeds twelve binary bits.

Compared with the known similar devices with comparable speed, the proposed device requires significantly less memory. For example, a memory of 65,536 words and 256 words is required to implement a known device with an accuracy of twelve binary bits. 4096 words and 64 words are required for the realization of the proposed device with the same accuracy; consequently, the technical implementation of the device does not encounter difficulties, since all the blocks are commercially available in integral form. The device can be made in the form of one LSI

The proposed device combines the requirements of maximum speed and optimal use of equipment, has a uniform and regular structure. Using the device is advisable as a specialized computing unit for performing the operation of calculating exponential-power functions at various baseline values in real time and at high frequencies this operation.

Claims (2)

1. USSR author's certificate 369565, CP. CJ 06 T - 7/38, 1970 2. USSR author's certificate number 321844, kp. G 11 B 5/00, 06.71,