SU551640A1 - A device for comparing the frequency of signals - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used in the implementation of technical means of information exchange.

A device for measuring the frequency of input signals is known, comprising a measured frequency converter, a device defining a set time interval, a comparison circuit.

Input Frequency Measurement

is done by converting the frequency of the input screens into a time interval and comparing it with a predetermined interval.

The disadvantage of this device is the presence of complex frequency converters and comparison circuits, as well as the inability to change the specified interval by software.

A device for comparing the frequency of signals is known, comprising a synchronization unit, an interval setting unit, an interval setting unit, an input signal selection unit, AND, and NO elements.

However, such a device does not allow matching the frequency of the input signals with

set the appropriate signal, if the frequency of the input signals is more or less than the specified one, and also to change the specified frequency programmatically.

The aim of the invention is to expand the range of frequency comparison. This is achieved in that the input bus in the device is connected to the input of the first element I, the other input of which is connected to the output of the synchronization unit, and through the element IE to the installation input to the zero state of the first trigger, the installation input to the state one which is connected to the output the first element And the direct output of the first trigger is connected to the inputs of the second and third elements And, the other inputs of which are connected to the corresponding outputs of the synchronization unit, and the output of the second, element And is connected to the installation input into one The second state of the second flip-flop, the direct output of the first flip-flop is connected through the NOT element to the setup input to the zero state of the second flip-flop and through the input signal extractor unit to the installation input to the third flip-flop state and the input to the zero setting of the fourth trigger , the installation of the unit in which state is connected with the zero input of the third trigger and with the output of the interval setting block, which hoppers are connected to the output of the interval setting block, to the output of the synchronization block, to another the input block of the input and to the forward output of the first trigger trigger, the installation input in the unit with which stand is connected to the output of the third element I, the third input of which is connected to the inverse output of the second trigger, and the installation input to the zero state with the fourth output element I, whose inputs are connected respectively with the output of the synchronization unit and the output of the fourth trggera output, BTOpoii, the setup input to the zero state of which from the output with the output of the third And element and with the input of the interval setting block, another input to It is expensively connected to the second bus of the device, the direct output of the third trigger is connected to the output bus of the device. The drawing shows a block diagram of the proposed device. The device contains triggers 1 and 2, an input signal selection block 3, a synchronization block 4, an interval setting block 5, an interval setting block 6, triggers 7, 8 and 9, elements 10 and 11, elements 12-15, input buses 16 and 17, the output bus 18. The operation of the device for comparing the frequencies of the signals is synchronized with the first, second, third, and fourth clock signals, which are generated in turn and are shifted relative to each other by a quarter clock cycle. The device operates as follows. The input signal on bus 16, with a duration of at least one clock cycle, is received in trigger 12 by the first clock signal in trigger 7. In a single clock cycle there are four clock signals with a quarter clock duration, and only one clock signal can be present at any time clock step. From the direct output of the trigger 7, the signal is fed to the input of the input signal extracting unit 3 and to the first inputs of the K 13 and 3.5 elements, through which the trigger 9 is set up using the second clock signal, and the trigger 8 is set up via the third clock signal, the inverse output of which blocks re-setting Three Hera 9 through the element And 15. Simultaneously with the installation of the trigger 9, the signal from the output of the element And 15 is set to the O position of Tritter 2, prohibiting the reset of the trigger 9 through the element And 14 on the fourth clock signal, and set this interval of operation of the interval setting unit 6 through the interval setting unit 5 by code on the bus 17. The signal from the direct output of the trigger 9 is fed to the input of unit 6, allowing it to work on the third sync signal of the synchronization unit 4, and also goes to the input signal of the input selection unit 3 signal, allowing the passage of the input signal to the output of this block. Block 3 is constructed in such a way that the first sampling input signal does not pass to its output, and subsequent input signals pass to the output of this block when there is an enable signal at the forward output of the trigger 9. Resetting the permission signal at the direct output of the trigger 9 at the moment of passing The input signal through block 3 does not affect its passage. The passage of the input signal through block 3 is prohibited if the enable signal at the direct output of flip-flop 9 is reset before the appearance of the input signal. Resetting the input signal on bus 16 causes reset of trigger 7 and trigger 8 through the elements NOT 10 and 11, respectively. The trigger 9 remains in a single state, allowing the operation of the interval setting unit 6 and the input selection unit 3. If the input signal arrival interval is greater than the specified interval, before the next input signal arrives after the specified interval has elapsed, the overflow signal appears on the third clock signal, which overflows trigger 1 and sets trigger 2, for which one state the trigger 9 is reset the fourth clock signal through the element 14. Low level from the direct output of the trigger 9 stops the operation of the interval setting unit 6 and prohibits the passage of the input signal through the allocation unit 3 input signal to its output. The next input signal on bus 16 causes the same effect as described above. Thus, if the interval of the input signals is longer than the specified interval defined by block 6, then the trigger 1 is maintained in the zero state, and the bus 18 is outputted to zero until the interval of the input signals becomes less than the specified one set in block 6 If the input signal arrival interval is less than the interval set by block 6, the next input signal received in trigger 7 passes to the output of input selection block 3 and sets trigger 1 to position 1, trigger 2 to position O, The zero from the direct output of the trigger 7 and the second clock signal through the element 15 is set to position 1 flip-flop 9 and reset to the position o flip-flop 2, and in block 6 through the interval setting block 5 the interval specified by the code number on the bus 17 6 starts at the origin. In this case, the trigger O does not reset, the trigger 1 is maintained in a single state, the level of the unit signal is output to the bus 18, and with each successive input signal the initial operating conditions of the block 6 are set and so on until the input signal interval more than a specified interval. The interval setting block 6 is made as a normal G-bit binary counter with a poisoned counting input that generates an overflow signal as an output signal when the counter is filled, each bit of which is connected to the unit 5 of the unit the interval for entering into the counter the initial code number of the interval arriving on the bus 17 from the external register. The code number of the interval is entered into block 6 paraphase through block 5 of the interval setting. A device for comparing the frequency of signals, in contrast to the known ones, allows one to quickly monitor changes in the frequency of input signals with respect to a given frequency and, depending on this, generates a corresponding signal and send it to a device that perceives input signals and change its mode of operation. and also programmatically set the required frequency for matching the frequency with the input signals. Introducing four triggers into the device, the operation of which is synchronized by the synchronization unit, allows frequency comparison without the use of frequency converters and a comparison circuit. F o o m u m o l o ome a device for comparing the frequency of signals, with the synchronization block, the interval setting block, the interval setting block, the input selection block, AND elements, NOT. This is so that, in order to expand the range of comparison, the input bus in it is connected to the input of the first AND element, the other input of which is connected to the output of the synchronization unit, and through the HP element to the installation input ; to the zero state of the first trigger, the input of which is set to one state is connected to the output of the first element And, the direct output of the first trigger is connected to the inputs of the second and third elements And, the other inputs of which are connected to the corresponding outputs of the synchronization unit, and the output of the second element And connected to the installation input to the single state of the second trigger, the direct output of the PB trigger is connected via the UE element to the input of the installation to the zero state of the second trigger and a caraz selection block of the input signal the installation of the third flip-flop unit and the set-up of the fourth flip-flop to the zero state; the output of the synchronization unit, to another input of the input signal isolation unit and to the forward output of the fifth trigger, the input of installation B whose unit state is connected to the output of the third element I, the third input of which is connected to the inverse output of the second trigger, and the setup input to the zero state — with the output of the fourth element I. whose inputs are connected to the output of the synchronization unit and the direct fourth trigger; the second input of the installation to the zero state is connected to the output of the third And element the interval setting unit, whose raw input is connected to the second bus of the device, the direct output of the third trigger is connected to the output mud of the device.