SU544135A1 - Binary Pulse Counter - Google Patents

Description

The output of the distributor is connected via the second key to the zero input of the first trigger, the first input of the element I and the counting input of the second trigger, the zero output of which is connected to the control inputs of the first additional keys, the unit output to the control inputs of the additional keys and the second input of the element And, the output of which is connected to the counting input of the trigger n of the same bit

The drawing shows a structural diagram of the proposed binary impulse counter.

The binary pulse counter contains the distributor 1, the first three outputs of which are directly, and the fourth through the switch 2 is connected to the counting inputs of the flip-flops 3 of the corresponding first four bits of the counter, the outputs of which through the relay 4 are connected to the first inputs of the additional switches 5 and 6, the second inputs of zero and single trigger outputs, respectively, the counting input of the trigger 7 is connected to the output of the key 8, the zero input of the trigger 9 and the first input of the element 10, the second input of which is connected to the single output trigger 7, and an output - with a counting input of a fifth trigger discharge. The first inputs of the keys 2 and 8 are connected to the fourth output of the distributor, and the second to the zero and single outputs of the trigger 9, respectively, the device input 11 is the input of the distributor 1, the outputs 12 are grouped in a certain way the outputs of the additional keys and the outputs of the relay 4 of the trigger 3 start with a trigger of the same rank.

The operation of the device is as follows.

Initially, the device is reset, in which the triggers 7 and 9 are in the zero state, the triggers of the second, third, and fourth counters are in the unit state, and in the first bit of the distributor 8 the unit is written. Therefore, the following binary number is stored in the initial state in the counter:

011100 ... oh.

The additional keys 5 are open, and the binary number 0111 is removed from their outputs.

Each pulse arriving at input 11 converts distributor 1 from position 4 to (-i + 1) -th. As a result of the arrival of the first three pulses to the input 11, one pulse arrives at the counting inputs of the triggers of the first three bits.

The counting inputs of the flip-flops 3 are received alternately by one pulse, the fourth pulse is fed to the trigger input 3 of the fourth bit via the normally open key 2 and to the single trigger input 9 and sets it to the single state. The next three pulses from the outputs of the distributor 8 are fed alternately to the counting ones the trigger inputs of the first three bits, and the fourth through the key 9 opened by the trigger 9 enters the zero input of the trigger 9, the counting input of the trigger 7 and the first input of the element 10. The trigger 9 returns to the zero state, the output of the element 10 and the pulse is canceled, and the trigger 7 is moved to a single position. Trigger 3 and relay 4 do not change their state 1, but due to the fact that the second trigger 7 is in the single position and additional keys 6 are opened, the indications on the low-order outputs of the counter change.

Thus, although the readings of the first four bits did not change, a new binary number appeared on the counter code. The next eight pulses produce actions similar to those of the first eight pulses with the only difference that the eighth pulse, in addition to setting trigger 9 to the zero state, also goes to the counting trigger input of the fifth bit through the element 10 and brings the trigger 7 to the zero state In this case, additional keys 5 are opened and through them the output information from the triggers of the first four bits is read. Thus, the generous pulse sets the triggers of the first four bits to the initial state, and the trigger of the fifth bit is set to one. The function of the device is reflected in the table.

As can be seen from the table, the readings of the first four bits require decoding. Starting from the first bit, the device works like a normal binary counter.

Changing the order of information output from the first four bits allows the speed to be doubled.

Original

from the state

14

from

11110

YOUTH

10010

10,000

ooooh

01000

01100

01100

eight

11,100

9

10,100

Yu

1OOOO

eleven

10010

12

0001О

13

O1O1O

14

15

from

sixteen

01111

15

11110

10110

13

10010

10,000

about

00000

01000

6

01100

11,000

eleven

11010

ten

01010

00010

00110

00100

1010О

11,100

01111

thirty

Claims (2)

1. USSR Author's Certificate No. 301858, H 03 K 23/24. claimed 13; 10.69. 2. USSR author's certificate hsi 381171, N OZ K 23/24, claimed 13. 09.71 {the most typical type). 12 12 J2 12X 12 12 f2 12 12 oo99OOOO9 u R -one and / x // // / I J