SU499652A1 - Multiphase pulse generator - Google Patents

Description

one

The invention relates to a pulse technique.

A multiphase pulse generator containing a push-pull sawtooth voltage generator made on two transistor current stabilizers with integrating capacitors, emitter repeaters on bipolar transistors with resistive voltage dividers in the transmitter circuits, whose transistors bases are connected to feedback circuits, is known MOS-type transistors, structurally located on the common, their substrates, and output pulse shapers.

A disadvantage of the known generator is the insufficient accuracy and linearity of the variation of the parameters of the output signals.

The aim of the invention is to increase the accuracy and linearity of changes in the parameters of the output signals.

This goal is achieved due to the fact that in the proposed generator additional shapers of output durations and delays are introduced, made on four MOS type transistors structurally placed on one substrate, and the gates of MOS transistors of additional shapers are connected in pairs to the corresponding outputs of resistive voltage dividers .

A schematic diagram of the described generator is shown in the drawing.

The generator consists of a two-stroke generator 1 of the sawtooth voltage, built on two symmetrical current stabilizers, including bipolar transistors 2, 3, diode 4, conduit 5, 6 resistor 7, and resistors 8-10, emitter repeaters on bipolar transistors 11, 12 voltage dividers and resistors 13-17 and 18-22, feedback circuits on MOS transistors 23, 24 and 25-27 located on the same substrate, shapers of duration and delay of the output signals,

built and a MOS transistor 28-32, located on the same semiconductor substrate, diodes 33, 34, resistors 35-42, shapers 43-46 output signals. The generator works as follows.

When the power is turned on, the voltage on the capacitors 5, 6 at the initial moment of time is zero, transistors II, 12 are closed, the voltage on resistors 9, 17 is zero, while transistors 23, 25, 27 are closed, and 24, 26

are open.

The capacitor 6 and the base of the transistor 12 are connected through an open transition of the drain-source of the transistor 24 to the common zero bus, maintaining the closed state of the transistors

12, 25, 27. The capacitor 5, linearly charging, opens the transistor 11, transferring the generated sawtooth voltage to the delnyel of resistors 13-17, while the linearly increasing voltage on the resistor 17 reaches the threshold voltage of the transistor 23, opens it, and the gates of transistors 24, 32 through an open transition drain-nstok transistor 23 are connected to the common bus, closing the transistors 24, 32. Before the capacitor 6 is linearly charged, opening the transistor 12, transmitting the generated sawtooth voltage to the divider from the resistor in 18-22, while the linearly increasing voltage across the resistor 22 reaches the threshold voltage of the transistor 25, opens it by connecting the gate of the transistor 26 through the open drain-source junction of the transistor 25 to the common zero cable, closing the transistor 26. High level the negative drain voltage of the transistor 26 enters the gate of the transistor 27, opens it by discharging the capacitor 5 through the open drain-source junction of the transistor 27, the transistor 11 is closed; at the same time, the sawtooth voltage on the resistor 17 drives up to zero, closing 25 transistor 23. The high level of negative drain voltage of transistor 23 goes to the gates of transistors 24 and 32, opens them, quickly discharging the capacitor 6, and transistor 12 o closes. The resistor 22 drops to zero, closing the transistor 5. The high negative voltage level of the drain of the transistor 25 goes to the gate of the transistor 26 and opens it, at 35 this the transistor 27 closes and the capacitor 5 starts to linearly charge, then process of repeated. The linearly increasing voltage on the divider of resistors 13-17 reaches the threshold-40 voltage of transistor 28, opens it, connecting the input of the driver 44 through the open drain-source junction of the transistor 28 to the common zero bus, while the output of the driver 44 is formed - 45 whom the zero of the output signal with a small front value. Simultaneously, the linear voltage across the resistors 16, 17 reaches the threshold voltage of the transistor 23, opens 50 of it, connecting the input of the driver 44 through the open drain-source junction of the transistor 29 to the common zero bus, while the output of the driver 43 forms a logic zero level with small the size of the front. 55 When capacitors are quickly discharged, transistor 11 closes, creating a zero voltage on the divider of resistors 13-17 and gates of transistors 28, 23, and high levels of negative voltage arrive at the inputs of 60, 43, 44 levels of logical unit of output signals with a small front value. The linearly increasing voltage at the isolator of resistors 18-22 ,, time shifted, reaches the threshold voltage of transistor 30, opens it, and the input of the imaging unit 45 connects through the open junction drain to source of the transistor 30 I will form at the output a logical zero level of the output signal with a small front value. A linearly increasing voltage across the resistors 21, 22 reaches the threshold voltage of the transistor 31 and opens it, and the input of the shaper 46 through the open transition drain-source of the transistor 31 is connected to a common zero bus, forming at the output a logical zero level of the output signal with a small value front. When capacitors are quickly discharged, transistors 30, 31 close, and transistor 32 opens, connecting inputs of drivers 44, 46 through open diodes and open drain-to-source junction of transistor 32 to a common zero bus, maintaining a logic zero level at outputs of drivers 45, 46. A linearly increasing voltage across the resistor 17 opens the transistor 23, connecting the gates of the transistors 24, 32 to the common zero bus, the transistors 24, 32 closing, closing the diodes with a high level of negative voltage, while at the inputs of the formers 45, 46 pos high negative levels fall, forming at their outputs levels of logical units with a small front value, since the transistors 23, 25 are simultaneously on the same substrate, and the transistors 28-31 on the other and are connected to different dividers, the time ratios of the output delays generated pulses remain constant. The generator frequency is tuned by varying the magnitude of the charging currents of the capacitors using a resistor 7, and changing the durations and delays of the output signals by switching the gates of transistors 28-31 to the corresponding inputs of the resistor dividers and 18-22. Ph o m u l a and 3 o b e e – n and a multiphase pulse generator containing a push-pull saw-tooth voltage generator made on two transistor current stabilizers with integrating capacitors, emitter followers on bipolar transistors with resistive voltage dividers emitters. the transistor bases of which are connected by feedback circuits from MOS-type transistors, structurally located on common substrates, and output pulse drivers, characterized in that, in order to increase the accuracy and linearity of the output parameters, it introduces additional duration and output delays performed

on four MOS-type transistors, structurally placed on the same substrate, and the gates of the MOS-type transistors of additional drivers are connected in pairs to the corresponding outputs of resistive voltage dividers.