SU482805A1 - A device for recording information in the RAM - Google Patents

Description

one

This invention relates to memory devices.

A device is known for transferring information to a RAM, which contains a pulse generator, an input information block, a code sensor connected to a control circuit, a switch connected to a register of 150 M coordinates, an information register.

With integer speed gains, the proposed device contains an additional address counter, a trigger and a comparison circuit whose inputs are connected to the outputs of the address counter and the coordinate register, and the output to the single trigger input, another input and output of which is connected to the commutator, the inputs of the additional address counter connectors to the outputs of the coordinate register and the switch, and its bit outputs to the bit outputs of the address counter, the output of the pulse generator is connected to the input of the information block, the output of the control circuit is connected to the input ol coordinate register.

The drawing shows a block diagram of the proposed device for accessing information in the operative memory.

The device contains a generator of nannulses 1, an input information block 2, for example, a plate, on the coordinate zero of which a stencil is superimposed, a sensor of codes 3 equipped with

the input button (not shown in the drawing), control circuit 4, registrar coordinate 5. switch 6, 1 format register 7, address counter 8. comparison circuit 9, trigger 10, additional address counter 11.

The inputs of the comparison circuit 9 are connected to the outputs of the comm line 8 n register 5, and now we go to one input of the trigger 10, the other input and output of which are connected to the switch 6. The inputs of the counter 11 nodes are connected to the register output 5 of the switch 6, and its bit outputs - to the bit outputs of the counter 8, the output of the pulse generator 1 is connected to the input of the unit 2, the output of the controller 6, 4, with the input of the register 5.

The control of the spacing (zormats1N1 is otshlttstvayutsya by focusing on the secondary coordinate code of the squares of the coordinate grid of the stencil. The coordinate grid is divided into three main zones; the address zone, the symbol zone, and the installation zone of the direct work. In the squares of the zone of symbols., Symbols are shown, the code KOTOpi) ix can be written in one-way mode. In the zone of installation of operating modes, the ir mogolpiki is represented by the names of operating modes.

To read the coordinate code of any square of the coordinate grid, it is necessary to combine the pointer of the sensor of codes 3 with this square, and then press the button of the sensor of codes 3.

The following is the order of the operator in the main operating modes.

After setting the character codeop entry to the address, the operator first reads the address code in the address zone of the coordinate grid of block 2. This code from the coordinate register 5 is entered into the address counter 8. Then the operator reads the character code, which from the coordinate register 5 is entered into register 7, and then in memory

After setting the byte writing mode, the operator first reads the code of the starting address of the selected array of memory cells. This code is entered into the address counter 8. Then the operator reads the code of the characters, which is transferred from register 5 to register 7, and then to the memory. Before reading the next character code, the address counter 8 changes its code to "1 under the influence of the signal from switch 6. After setting the read mode from the memory, the operator reads the code of the selected square in the address area, then press the sensor button 3 to read the square code at other addresses not necessarily.

After setting the write mode of the same byte to any array of memory cells, the operator reads the character code that is entered in register 7.

The operator then reads the code for the starting and ending address of the array of memory cells t1. In this case, the switch 6 begins to work many times, each time increasing the code in the counter of address 8 by one. The termination of the operation of the switch 6 and occurs when the code of the address counter 8 is compared with the code of the coordinate register 5. In this

The time comparison circuit 9 supplies a signal to the trigger 10, which controls the end of operation of the switch 6.

After setting the non-spacing mode of the contents of one array of memory cells to another, the operator reads the code for the initial address of the first and second arrays, and then reads the code for the final address of the first array.

At that, the switch 6 starts to work repeatedly, each time causing the bytes to be output from the memory to the register 7 by the code of the address of the additional counter 11 and the reverse input of the bytes to the memory by the code of the address counter 8.

The termination of the switch 6 operation takes place at the moment of comparing the codes of the address counter 8 and the coordinate register 5.

Subject invention

A device for recording information into an operational memory comprising a pulse generator, an input information block, a code sensor connected to a control circuit, a switch connected to a coordinate register, an information register and an address counter, characterized in that, in order to increase speed, it contains an additional address counter, trigger and comparison circuit, whose inputs are connected to the outputs of the address counter and coordinate register, and the output to one trigger input, the other input and output of which are connected to the switch rum, additional inputs connected to the address counter and outputs coordinate switch register, and outputs it The discharge -k discharge dnym outputs address counter imiulsov generator output coupled to an input of the information unit, control circuits output - to the input coordinate register.