SU460504A1 - Digital ac bridge - Google Patents

Description

one

The invention relates to the field of electrical measuring equipment and can be used to measure the components of complex resistances.

In the known automatic digital bridges of alternating current containing a bridge circuit, a sinusoidal voltage generator, balancing units, null organs and digital display units, the speed is limited by the presence of a transient process when switching balancing elements in the bridge circuit.

The aim of the invention is to increase the speed by setting the moment of switching the sum of two voltages so that at the output of the switched circuit the voltage is equivalent to the steady-state voltage. This goal is achieved by introducing a code converter, discrete resistor dividers, a phase-shifting unit, a subtraction unit, an adder, and a control pulse shaping unit.

The block diagram of the digital bridge is shown in the drawing.

The following components are included in the circuit: sinusoidal voltage generator 1, digital indication blocks 2 and 3, balancing blocks 4 and 5, bridge 6, code converter 7, phase shifting block 8, discrete

resistor dividers 9 and 10, adder 11, null-bodies 12 and 13, subtraction unit 14, and control pulse-shaping unit 15.

The device works as follows.

The voltages corresponding to the forced voltages that are set at the output of the balancing circuit after each switching are formed using a code converter 7, a phase shifter unit 8, discrete resistor dividers 9 and 10, and an adder 11. At the output of the discrete resistor divider 9, the synphasic component of the formed voltage (p, and the output of the divider is 10 quadratic component (/ c f {pf. Codes 4 and 5 of the balance, determining the amplitude and phase of the voltage removed from the counterbalance circuit bridge circuit 6 after each equilibration step, code converter 7 is converted so that the output of the discrete resistor divider 9 produces a voltage Un L / coscp, and the output of the divider 10 voltage L / c - Usincp. At the output of the adder 11, a voltage with amplitude is obtained

and.

U-V U - {- ul and phase 9 arctg

and

R. The generated voltage does not experience transients, since the dividers 9 and 10 do not contain reactive elements. The code converter 7 is constructed in such a way that the output of the adder 11 generates a voltage that will occur at the output of the balancing circuit included in the bridge circuit 6 after the next switching. From the output of the adder 11, the generated voltage enters the subtraction unit 14 and is subtracted with the voltage of that branch of the bridge circuit 6 in which the switching is performed. The moment of equality of the difference signal bullet is the moment when there is no transient in the balance circuit. The differential voltage is supplied to a clock-forming unit 15, in which the formation of narrow pulses occurs at the moments of zero crossing of the differential voltage, and these pulses control the balancing blocks 4 and 5. The balancing of the bridge circuit 6 is performed by switching the elements included in the branch not containing the measured impedance. Since the switching of the balancing elements is carried out with a clock frequency developed in accordance with the requirement of no transients, the voltage removed from the balancing beams; twi that does not contain an exponential component goes to the inputs of the cul-organs 12 and 13, which due to the absence of transients after commutation of balancing elements have the ability to make a voltage comparison immediately after each commutation. Nullorgans 12 and 13 control the operation of balancing blocks 4 and 5, which, in turn, control the switching of balancing parameters in the bridge circuit. The subject of the invention is an AC digital bridge containing a sinusoidal voltage generator, a bridge circuit, equilibration blocks, null organs and digital indication blocks, characterized in that it is equipped with a code converter, discrete resistor dividers, phase shifter, block subtracting, an adder and a control pulse shaping unit, the first and second inputs of the code converter being connected respectively to the first outputs of the first and second balancing units and the first and second outputs of the code converter are connected respectively to the first inputs of the first and second discrete resistor dividers, the second inputs of which are connected to the sinusoidal voltage generator of the first resistor divider directly, and the second resistor divider through the phase shifter, the outputs of the first and second resistor dividers with the first and second inputs of the adder, the output of which is connected to one of the inputs of the subtraction unit, the second input of which is connected to the first input of the first and a second zero-body subtractor output is connected through the block forming control pulses to the first inputs of the first and second equilibration blocks.