SU432676A1 - ANALOG-DIGITAL CONVERTER - Google Patents

Description

one

The invention relates to a digital electrical measuring technique, and it can be applied in converters of voltage to digital code, operating under add-on conditions for HTV.

The analog-to-digital converter is known, which contains a comparison device, a control device, a distributor, a basic digital, analog-digital converter, a reversible counter-count, a counter, a remote control, and an "I.

However, in the known device, a predetermined number of measurement results involved in the integration is set a priori, as a result of which the conversion error varies from measurement to measurement. With the mini- mization of the indicated log-break and the random nature of interference, the number of integrable results increases with the growth of equipment and time of measurement.

In order to improve the accuracy of converting DC voltage under conditions of additive Interference, reducing the conversion time for digital IN1 integrated results and measurements, the proposed device additionally introduces an adder, a reversible counter for a given permissible error from interference, a D / A increment converter and a logic circuit whose inputs are connected to

2

the corresponding outputs of the distributor, decoder and counter, and the outputs with the inputs of the distributor and the digital-analog converter of increments, the outputs of the latter are connected to the inputs of the adder-average and the input of the emergency device to which the output of the main digital-analog converter is connected, younger The main digital-to-analog converter converter is connected to the output i and the adder-average, the output of the sum of the matrix-average, is connected to the input of the reversible counter, and the input to the output of the reversible counter for a.nnoy allowable pogreschnosti from .pomehi having inputs za.ny communication with down counter outputs.

The drawing shows a block diagram of the proposed device.

The device works as follows.

The command "Starting begins the process of analog-to-digital conversion, in which the comparison device / participates, the distributor 2 clocks, the basic digital-to-analog converter 3 and the control device 4. As a result, the basic digital-analog converter 3 ( on the register of memory included in it (counter), a co.d is generated, corresponding to the sum of the measured voltage and the random value of addity.

 + a also determines the value of co.p1: on-voltage, which is applied to the input of the comparison device 1.

Then, a repeated measurement is performed at the increments of the additive interference (since the measured voltage does not change during the measurement) with respect to the value recorded in the main digital-to-analog converter 3. The increments measurement is performed by the "start coding" signal increments from counter 5 through logic 6 using the device 4. The number of bits that are involved in the measurement of increments in the 2 clock pulse distributor and the digital-and-analog converter 7 increments, It is the code of the reversible counter 8, which through the decimator 9 controls the operation of the logic circuit 6. The latter controls the lower bits of the distributor 2, the clock impulses of which through the logic circuit 6 arrive at the digital-analogue converter 7 increments. After each increment measurement, the number of which is determined by the counter code 5, its code is rewritten into the accumulator 10, taking into account the sign.

Total increment value

| And ..

stored in the adder-breeder 10. Thereafter, an L-brief re-measurement of increments and subtraction takes into account the sign of the received codes from the code recorded in the adder-averager 10, resulting in a code corresponding to the difference of two sums

2 dB

-EAt / l, /.-1 -1

Then from the control unit 4 and from the counter 5 signals are sent to the logic circuit "AND 11, the output signal of which shifts the code in the adder-interceptor 10 by the number of bits, proportional to / g, which is equivalent to dividing by

The average resolution of the transmissions with the help of the average mass compressor 10 is compared with the admissible logfire from the interference E, which is specified as a code in the reversible counter 12, specifying the permissible error from the interference. If the spread is larger than the specified permissible error from the interference, then I reversed from the reversing counter 8, which corresponds to the increase in the number of averaged results, and if the averaged difference is smaller, then 1 is added to it, which corresponds to an increase in the number of averaged results.

Then, the averaging of increments occurs, the number of which varies in severity to two and the usual amounts of increments. The averaged value is summed with the code recorded in the main digital-to-analog converter 3. This introduces an amendment that reduces, influences and interferes, after which the result of the conversion is output with a predetermined error rate, and the measurement cycle is repeated

iodac signal zalusk.

The number of averaged increment results is variable, depending on the dissipation of the input interference and the set of permissible error on the interference g. Adjustment

the values of n on the reversible counter 8 occurs in accordance with the following procedure.

“2 1 + An sign A,

where n is the number of the averaged number of my results at the time moment; P2 is the value of the number of averaged results at the time instant.

+ 1 A o

sign D - 1 D O

A | iAL / -S А / 7,., / 1 i-iThis procedure is implemented with the HELP of a reversible counter, controlled by the accumulator 10, determining the

Comparing the averaged difference with the permissible error from the interference s, the increase or decrease in the number of average results in the reversible counter 8. During the 77 adjustment cycles, a certain average value / JQ is established on the reversible counter 8, which determines the optimum number of averaged results. Before each cycle of averaging, the code from the reversible counter 8 is rewritten into counter 5, determined

This is the number of incremental coding launches.

In a reversible counter, 8 bits, corresponding to a predetermined maximum and minimum values of n, are generated by control pulses that change the value of a predetermined permissible error from the interference on the reversible counter 12 to a predetermined permissible error from the interference to the larger or smaller side, which allows to receive. reliable measurement results under conditions of increasing interference, as well as results with less inconsistency of measurement under conditions; and x decreasing bandwidth.

The number of averaged bit sizes depends

from the number of averaged results p, and with a change in the number p, the reversible counter 8 through the decryptor 9 and the logic circuit 6 controls the number of polled bits of the Digital-to-analogue. preo (digester 7

increments, which allows to increase the speed of the converter.