SU432564A1 - DEVICE FOR CHECKING * FUNCTIONING OF ANGLE CONVERTERS — CODE - Google Patents

Description

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The device relates to automation and computing technology and is intended for testing angle-to-code converters.

A device that allows to determine the correctness of the alternating code of the test transformer and the value will be mistaken in the output code and containing the converter of the pulse clock into the potential multivibrator, counters, triggers, decoder, differentiating circuits, logic circuits, display unit. It is characterized by the incomplete accuracy of the result of checking the correctness of the function of the converter. This is explained by the fact that the correct sequence of the change of the output code of the converter does not constitute a basis for concluding that it is functioning properly. Another IM condition must be that the output code must correspond to the specified angular position of the shaft and converter.

The aim of the invention is to increase the reliability of the angle-code transducer test results.

The proposed device makes it possible to check the output code under the conditions of its strict visibility to the angle of rotation of the converter shaft, as well as in case of an incorrect output code, to determine the magnitude and sign of its error. The device is designed to test the angle of the code in the production of them (pr-ode, standard, etc.), and also, taking into account the possibility of setting different values - the time shift reference and real signals, can be used in various studies converters.

FIG. 1 shows the functional scheme of the device; in fig. 2 - timing diagram of a - real p b - reference signals and the notation adopted: / - test angle-code converter; 2 - uniform speed; 3 - the first decoder; 4-8 — Circuits 9-12 —Circuits 13 and 14 — Inverters; 15 - reversible counter; 16 - counter; 17 - the second decoder; 18 - frequency divider; 19 - generator; 20 p 21 - triggers; 22 - one-shot;

23-25 - delay circuits; 26 is a differentiating scheme; 27 - registration block.

The initial angle-code converter / is connected by its shaft with the drive 2 and equal to the dimensional speed. The output buses of the converter are connected to the first decoder 3 of the initial code, as well as to the inputs of the circuits “AND 4. Their other inputs through the inverter 13 are connected to the outputs of the bits of the counter 15. The output of the decoder 3 is through a delay circuit

23 is connected to the trigger input 20, the corresponding output of which is connected to circuit 6 and 6, which is a valve in the circuit of generator 19 and the input of frequency divider 18 The first output of frequency divider is connected via delay circuit 24 to the input of the distributor // whose output is connected to tert1 to them | the inputs of the circuits “AND 4, through the circuit“ OR 12 with the input of the circuit “AND 5, another input of which through the inverter M connects to the output of the circuit J”, the inputs of which are connected to the outputs of the circuits “AND 4. The second output of frequency divider 18 is connected to the input of the circuit "And /, the second input of which is connected to the output of the trigger 21, in which the first input through the differentiating circuit 26 is connected to the output of the circuit" OR 9, and the second input to the last output of the diaphragm 17 The output of the circuit "And 7 is connected to the input of the Count / 6, with which Connected de-embedder / 7 outputs of which are united by the state of the schemes "OR W and // into two groups. In this case, the output of the circuit “OR W is connected to the second pin and // is connected to the subtracting input of the reversal 1Tto; G - P ° deshpFratora / 7 is connected to the inputs of the corresponding circuits“ AND 8, the other inputs of which are connected to the output of the inverter M, and the outputs to the inputs block registration 27 of the test result. Test converter / drive into uniform rotation by drive 2 A natural binary code is generated at the output of the converter. When some initial code appears, the decimator 3 is triggered (see Fig. 2, point L) and the trigger 20 is moved with a certain delay (see Fig. 2, point B). The initial state of the trigger 20 is set and the beginning of the test. As a result, the circuit 6 opens, and the pulses of the generator 19 begin to arrive at the input of frequency divider 18. As overflow occurs, signals that are reference signals appear at its output, which arrive through the circuit OR 12 at the input of the addition of the reversible counter 15. Comparison of real the converter code / and the reference code generated by counting the pulse-frequency-stable pulses in the reversible counter 15, occurs during the time of the single-oscillator 22 working at a specified time interval from the moment of the formation of The alternate reference code (see Fig. 2, points C, D, D.) If the converter / p codes of counter 15 are equal, then due to the action of inverters 13 at the outputs of the AND 4 circuits and the output of the OR 9 signal, there is no signal. In this case, the signal appears at the input of the circuit "And 5", and with the arrival of the signal at its other input from the output of the frequency divider / 5, a signal appears at the output about the correctness of the transducer code / at a given angular coordinate. The delay circuit 25 is necessary to prevent failures due to the end time of the triggered 1 circuits and 5 and the inverter 14; The delay circuit 24 is necessary so that the comparison of the inverter codes / and counter 15 takes place after the transient processes in the counter / 5 are completed at three types of the next pulse from the output of frequency divider 18. In the considered variant, the matching of the compared codes after the one-shot 22 of a given time interval does not change in the operation of the circuit does not occur. When comparing the converter / code and the counter 15 do not match, when the one-shot 22 is triggered, a signal appears at least on the output of one of the AND 4 circuits and then the output of the OR 9 circuit is generated. trigger 21, as a result of which the circuit 7 opens. Pulses from a different, higher frequency output of the frequency divider 18 begin to arrive at the 1-count input 16. As each new pulse starts, a signal is output at any output of the decoder 17. All outputs excluding the last Inen by means of the schemes "OR 10 n // into two groups, corresponding to cases of increasing and decreasing the number in the counter 15. With the number increasing in the counter 15 from zero to some value on a faster time scale, a temporary increase in the number in the counter 15 occurs, and then its decrease by 1, 2 ... binary units, returning to the initial state. At the same time, with each new code, the counter 15 passes its comparison with the code of the converter /, since the one-shot 22 provides a signal to the third inputs of the “I 4” circuits. For each mismatch of the codes, there is no signal at the output of the inverter 14, none of the “And 5” circuits it works. If at some modified reference code the combination of this code with the converter code / occurs, the signal at the output of the AND 4 and OR 9 circuits disappears, which leads to its appearance at the output of the inverter 14 and the corresponding inputs of the AND 8 circuits. Depending From what number at this moment is recorded in the counter 16 and, consequently, what output of the decoder 17 is excited, one of the “AND 8” schemes is triggered, corresponding to the magnitude and sign of the error in the test transducer's KO.ie. Then, when a certain number is reached in the counter 16, a signal appears at the last output of the decipher 17, which returns the trigger 21 to the initial state. In this order, the reversible counter / 5 returns to its original state, in which the compared codes do not match. This means that the output of the "ILR1 9" circuit has a signal. However, in this case, the trigger 21 does not change its state, since it is due to the differentiating circuit 26. reacts not to the presence of a signal, but at the time of its occurrence. After working with the one-shot 22 of a predetermined time interval, the signal at the output of the circuit “OR 9 will be output. When comparing the codes in the next angular coordinate of the shaft and the transducer, at the time of the operation of the odomotor 22, provided that the compared codes do not match, the output signal of the OR circuit appears again, as a result of which the differentiating circuit 26 is triggered and the operation of the device is repeated.

Note that the circuit 25 should have a small delay in order to exclude the operation of the circuit “And 5 if the converter code coincides with the temporarily changed counter code 15.

As can be seen from FIG. 2, by varying the delay time of circuit 23, it is possible to vary the conditions of the test, equaling the requirements for correct functioning of the angle-code converter under test.

Subject invention

A device for checking the operation of angle-code converters containing a uniform speed drive with which the shaft of the test converter is connected, the outputs of which are connected to the inputs of the first decoder and the first inputs of the first And circuits, the second inputs of which are connected through the first inverters to the outputs of the reversible counter bits , and the outputs through the serially connected first OR or second inverter circuit are connected to the first inputs of the second AND circuits, the outputs of which are connected to the corresponding inputs of the register unit AI, and the second inputs -

with the outputs of the second decoder, the inputs KoToj) CTo are connected to the outputs of the counter bits, and the outputs are connected to the inputs of the second) o: i and the third OR circuit, the output of which

Connected to the subtraction input of a reversible counter, characterized in that, in order to increase the reliability of the angle-code test results, a stabilized generator is introduced into the device

pulses, triggers, one-shot, frequency divider, delay circuits, a differentiating circuit and additional Pi and OR circuits, the output of the first decoder through an adjustable delay circuit connected to the input of the first trigger, the output ivOTOTo to the first input of the first additional circuit And whose second input is connected to the output of a stabilized pulse generator, and the output is connected to the input

a frequency divider, the first output of which is connected through the first delay circuit connected in series and the one-shot is connected to the third inputs of the first AND circuits, through the second delay circuit is connected to the first input of the second additional AND circuit, the second input of which is connected to the output of the second inverter and the corresponding input of the registration unit, and to the first input of the additional circuit “OR, the second

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the input of which is connected to the output of the second OR circuit, and the output to the addition input of the reversible counter, the second output of the frequency divider is connected to the first input of the third additional circuit And, output

which is connected to the counter input, and the second input is connected to the output of the second trigger, the first input of which is connected to the output of the first circuit through the dpferenzgfuil file and the second input to the last output of the second decoder.

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