SU427478A1 - RING COUNTER - Google Patents

Description

The invention relates to measuring and computing technology. The counter can be used in various automatic, logical and 1I1 information devices.

Ring counters on current switches with emitter connections are known, consisting of an odd number of cells in which the bases of the first transistor switches of all the cells are connected together and form the counting input of the circuit.

The operating frequency of the known counters with the same parameters of the transistors of the keys is the higher, the greater the switched current within permissible limits. The current through the cross-linking element should more than double the currents of the transistor switches. This leads to the fact that at the same values of the limiting currents of transistor switches and cross-linking elements, or with their identical limiting mosh, but which is especially characteristic of transistor microelectronic components of electronic circuits, the current can flow through the transistors of current switches by half . Therefore, the circuit does not allow to increase the meter speed by increasing the switching current.

Since the stabilization voltage on the cross-connect elements is 5–8 V, and the power supply voltage of the circuit must more than double the stabilization voltage of the cross-connect elements, a significant mosch is dissipated on the collector resistance of the transistor switch.

As a result of the need to pass a current, more than twice the currents of transistor switches, through the cross-cell element of the cell, the known circuit has a high level of logic zero, which in some cases makes it difficult to decipher the code of the number recorded in the counter .

The purpose of the invention is to reduce the consumed power, increase the speed of the circuit and reduce the voltage level of the logic zero, because the collector of the first transistor of the key of the proposed meter counter is connected to the base of the second transistor of the cell through a transistor connected according to the circuit with it has a collector, the meter outputs being the load resistances of the keys.

Pa figs. 1 shows the basic scheme of the counter with a conversion factor of 3; pas figs. 2 shows the timing diagrams of the transitions of the scheme.

The counter contains the first and second current switches / 1 and 2i, Iz and, / s and 2 of the first, second and third cells, respectively; emitter shooters 3, 3, 3, emitter resistors of transistors 4i, 4, 4, load resistors of current switches 5i, 5, 5z, emitter resistors of emitter follower (2, 3.

In the initial state, at the first output of the counter circuit (Fig. 1), the zero voltage is set, at the second (-0.4) volts, at the third (-0.8) volts. For this, the transistors 2, 22, h of the current switches must be open, the transistors / 1, 1-2, 2z-closed. Since the base-emitter of silicon transistors at the junctions decreases the voltage (, c, then at the outputs of the emitter followers the voltages are set to: (0.7) 0; 2- (-1.1) o; 2 - (- 1.5 ) c. In order to preserve the initial state of the circuit cells, there must be an –il potential at the counting input of the circuit, 5

-1.1 8.

Thus, if the voltage at is kept at the counting input of the circuit, o is 1.3, the circuit in this state can be indefinitely long.

With the arrival of the first pulse, the input voltage drops to -0.9 volts. Therefore, the voltage at the base of the transistor / a becomes less than that at the base of the RZ transistor, and the ratio between the base voltages of the remaining pairs of current switches remains the same. This causes the current key / 2 to open, and the key Pg to be locked. At the first output of the circuit, a zero voltage is set, at the second (–0.8) V, at the third (–0.4) V, and at the outputs of the emitter followers 3i, 3, and 3h, respectively, 0.7, -, 5 and - 1.1 8. This circuit state is maintained for the entire pulse duration.

During the second half period of the input frequency, the voltage at the input of the circuit again becomes equal to -1.3 V, and since the voltage of transistor 2 was -1.1 V, the key / i opens and the key 2 | locked up. Now the voltage at the first output of the meter is set (-0.4) V, at the second (-0.8) V, at the third - zero. Voltages from emitter followers, which bias the output voltages of the circuit to the negative region by 0.7 volts, keep the circuit cells in this state until the next pulse arrives (Fig. 2). Therefore, when counting a single pulse, the zero voltage level in the meter moves from the first output to the third, after the second pulse to the second. After the third pulse, the circuit returns to its original state when the zero voltage is removed from the first output.

In the proposed scheme, the power dissipated by the cross-linking element is approximately half the power dissipated by transistor switches. This allows, through the redistribution of currents that previously flow through the elements of cross-links, to increase the currents switched by transistor switches.

Therefore, the proposed scheme has a higher speed than the known schemes. Let us estimate how many times the counter frequency has increased.

It is known that the propagation delay time is at the level of 50% of the logical unit for circuits on current switches

/. i + (o, 7cJ- + 0.5C.J--).,

where ty is the delay time, depending only on the parameters of the transistors;

C, - full capacity, connected to each output of the meter circuit;

Ci is the input capacity of the emitter follower;

E is the power supply voltage;

Vi is the voltage swing of a logical unit at the output of the circuit;

Pg-power dissipated by current switches;

Re-power dissipated by an emitter follower.

The best relationship between Pg and Re is the ratio. Therefore, the expression for ta can be rewritten:

, - /,; + - (0.7 s, i-Q) Ey ,.

Based on the timing diagrams in FIG. 2, it can be concluded that the minimum period of the input pulse frequency that can be fed to the counter is 2L. Therefore, the maximum frequency

.min

input pulses of the proposed counter can be determined by the formula

0.5I

one

prel

-y -,

- mipg, / - ,,

п rdsd -; - (0,7 Cj p-CL) EVI

50 or at t, P ,,,,, “(0.7 C, -; - CL} EV

, „,,,

/ mak

(0.7C, -Ci) fK,

where pg. - limiting power dissipated by current switches.

From the obtained expression it follows that the working frequency of the counter is twice as high as the counter frequency, made according to the scheme taken from the prototype.

In the proposed scheme, only one power source is required, and the voltage is two times less than the voltage of both sources required for the operation of the known circuit. Therefore, with the same switching currents, the power consumed by each cell is as much less.

Since the currents in the cross-connect elements of the proposed circuit have decreased and become equal to the currents of the emitter follower bases (/ bep), the ratio of the voltage levels of the logical unit ({/) and logical zero (f / o) increases in this circuit:

1 IK.I + / bk IK.l and

777 7

Q-bep bep

and for the case when / CL / EP, t / i

and,

One of the advantages of the meter circuit is also the possibility of its execution not only in the hybrid, but also in the solid-state version, and the output voltage levels of the circuit are in good agreement with the voltage levels of commercially available microcircuits on the current switches.

Subject invention

A ring counter on current switches made on emitter-connected transistors consisting of an odd number of cells in which the bases of the transistors of the first keys of all cells are combined and form the counting input of the ring counter,

and the collector of the transistor of the first key g of the cell is connected to the collector of the transistor of the second key of the i-1-cell and the load resistor, characterized in that, in order to increase speed, reduce power consumption and the voltage level of logic voltage, each cell ring counter contains an emitter follower, while the collector of the transistor of the first key of the j-th cell is connected to the base of the transistor

The second key of this cell is through an emitter follower transistor, the base of which is connected to the collector of the first key transistor, and the emitter is connected to the base of the second key transistor.

{Js

BS 3

0th

Rig /

-0.9 -1.3

sh, i

-a "-0.

: J