CA1066369A - N-bit register system using cml circuits - Google Patents
N-bit register system using cml circuitsInfo
- Publication number
- CA1066369A CA1066369A CA265,553A CA265553A CA1066369A CA 1066369 A CA1066369 A CA 1066369A CA 265553 A CA265553 A CA 265553A CA 1066369 A CA1066369 A CA 1066369A
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- CA
- Canada
- Prior art keywords
- reference voltage
- transistor
- transistors
- voltage means
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Shift Register Type Memory (AREA)
- Logic Circuits (AREA)
Abstract
Abstract The invention discloses basic current mode logic (CML) circuits which function as feedback latches. One embodiment of the latch is a circuit for storing an input data signal. An alternative embodiment of the latch is a circuit which performs an An/Or function on a plurality of input data signals and then stores the result. The latch embodiments may be combined to form register systems. One combination of latch circuit provides a basic component for a shift register wherein a simple clocking system is utilized to provide a built-in delay mechanism required for proper operation of the shift register.
Description
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Background of the Invention ~ield of the Invention The present invention relates generally to high-speed logic circuits for use in data processing systems and in particular to CML circuit designs for implementing storage and logical registers for said data processing systems.
Description of the Prior Art The evolution of electronic data processing systems has inextricably trended towards faster and more reliable systems. As part of this trend the various components used for assemblying said data processing systems have similan~ evolved towards smaller, faster and denser parts. One such part affected by this evolution-ary process is the working storage e].ement or register.
,`! The register function is notoriously old in the art: in response to control s~gnals, the register must store a bit (or bits) of data. A register system may include means ~or storing a plurality of bits in parallel. Alternatively 3 a register system may be designed serially such that it forms a shift register. If a register is buiIt with a feedback loop such that it continues to store the data until signalled to do otherwise, the register is sometimes referred to as latch.
Current mode loglc (CML) offers a relatively new circuit design technology for providing high-spee~, high-density electronic parts such as registers. ~ prior art CML register is described in U. S. Patent No. 3,514,640, issued February 3, 1967 to D. L~ Fett.
However, there is a need for a CML register circuit which could be produced on a semiconductor chip of higher density. Also there is
Background of the Invention ~ield of the Invention The present invention relates generally to high-speed logic circuits for use in data processing systems and in particular to CML circuit designs for implementing storage and logical registers for said data processing systems.
Description of the Prior Art The evolution of electronic data processing systems has inextricably trended towards faster and more reliable systems. As part of this trend the various components used for assemblying said data processing systems have similan~ evolved towards smaller, faster and denser parts. One such part affected by this evolution-ary process is the working storage e].ement or register.
,`! The register function is notoriously old in the art: in response to control s~gnals, the register must store a bit (or bits) of data. A register system may include means ~or storing a plurality of bits in parallel. Alternatively 3 a register system may be designed serially such that it forms a shift register. If a register is buiIt with a feedback loop such that it continues to store the data until signalled to do otherwise, the register is sometimes referred to as latch.
Current mode loglc (CML) offers a relatively new circuit design technology for providing high-spee~, high-density electronic parts such as registers. ~ prior art CML register is described in U. S. Patent No. 3,514,640, issued February 3, 1967 to D. L~ Fett.
However, there is a need for a CML register circuit which could be produced on a semiconductor chip of higher density. Also there is
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~ii63~9 the need for a pulse generation scheme for control of input and output of data from the register system. If properly designed, a pulse generation scheme could enhance the operating character-istics of the register system as well as make it more useful as a building block within data processing systems.
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Objects of the Invention It is an object of the present invention therefore to pro-vide an improved register system using CML circuit design.
It is another ob;ect of the present invention to provide ; `a CML register whlch includes an improved pulse generation scheme.
; It is another object of the present invention to provide an N-bit And/Or CML register system.
It is still another obJect of the present invention to . ~
provide an N-bit Master/Slave register system for use in a serial register.
; Other objects and benefits will become apparent from the following description of the preferred embodiment of the invention when read ~n conjunction with the drawings contained herewith.
., '!' Summary of the Invention ~'' The invention comprises current mode logic (CML) circuits , for a register which functions as a feedback latch. The reg~ster circuits include gates comprised of groups o~ transistors w1th commonly connected collectors. Similarly, the gates are also ', designed with shared resistors for enhancing their density charac-teristlcs. One of the register gates provide the latching function by having its output signal fed back to one of its inputs. The gates are clocked by clock signals sent to the data input gates and the complement of said clock 5~ sent to the latchlng feed-
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~ii63~9 the need for a pulse generation scheme for control of input and output of data from the register system. If properly designed, a pulse generation scheme could enhance the operating character-istics of the register system as well as make it more useful as a building block within data processing systems.
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Objects of the Invention It is an object of the present invention therefore to pro-vide an improved register system using CML circuit design.
It is another ob;ect of the present invention to provide ; `a CML register whlch includes an improved pulse generation scheme.
; It is another object of the present invention to provide an N-bit And/Or CML register system.
It is still another obJect of the present invention to . ~
provide an N-bit Master/Slave register system for use in a serial register.
; Other objects and benefits will become apparent from the following description of the preferred embodiment of the invention when read ~n conjunction with the drawings contained herewith.
., '!' Summary of the Invention ~'' The invention comprises current mode logic (CML) circuits , for a register which functions as a feedback latch. The reg~ster circuits include gates comprised of groups o~ transistors w1th commonly connected collectors. Similarly, the gates are also ', designed with shared resistors for enhancing their density charac-teristlcs. One of the register gates provide the latching function by having its output signal fed back to one of its inputs. The gates are clocked by clock signals sent to the data input gates and the complement of said clock 5~ sent to the latchlng feed-
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back gate.
One embodiment of the latch includes a single data input gate and a latching gate and stores either a single data input or the AND function of several data input signals. An alternative embodiment of the latch includes a plurality of data input gates and a single latching gate and performs an AND/OR function on a plurality of data input signals prior to storing the result.
These embodiments of the latch may be combined to form register systems. One combination of the latching register circuit provides the basic components (i.e. bit cells) for a shift register. This shift register includes a simple clocking system which provides a built-in delay mechanism for proper operation of the shift register.
Thus, according to a broad aspect of the present invention, there - is provided a current mode logic circuit responsive to complementary first and second clock signals for storing a logical AND function of a plurality of input signals, said circuit comprising: firstJ second and third reference voltage means, each of said reference voltage means producing a first, second and third voltage signal, said seconcl voltage signal of a level between said first and said third voltage signals; a first transistor with its base -. ~
coupled to said second reference voltage means; a second transistor with its base connected to recèive said first clock signals; a plurality of other transistors, each of sald other transistors having its base connected to receive one of said plurality of input signals, the collectors of said second ~ -and said other transistors commonly connected to said first reference voltage means; first resistive means commonly connecting the emitters of said first, second and other transistors to said third reference voltage means; a third transistor with its base connected to said second reference voltage means;
~, a fourth transistor with its base connected to receive said second clock signals; a fifth transistor with its base connected to the collector of said third t-ransistor, the collectors of said fourth and fifth transistors common-ly connected to said first reference voltage means; second resistive means commonly connecting the emit~ers of said third, fourth and fifth transistors ~ -4-.~,,~
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to said third reference voltage means; and third resistive means coupling the collectors of said first and said third transistors to said first reference voltage means.
The invention will now be described in greater detail with refer- :
ence to the accompanying drawings, in which:
Figure la is a logic diagram of the basic latching register of the . present invention;
Figure lb is a circuit diagram for implementing the latching register shown in Figure la;
Figure lc is a timing diagram which explains the operation of the .:.
circuit shown in Figure lb;
Figure 2a is a logic diagram of an AND/~R latching register of the present invention;
. Figure 2b is a circuit diagram for implementing the AND./OR latching register shown in Figure 2c;
.` Figure 3 is a block diagram of a ten-bit parallel storage register . system, an embodiment of the present invention;
`~ Figure 4 is a block diagram of a five-bit AND/OR parallel register sys~em, an embodiment of the present invention;
Figure S is a block diagram of a five-bit ~NDlOR Master~Slave .;~ . .
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parallel register system, an embodiment of the present invention, and Figure 6 is a block diagram of a three-bit shift register.
Description of a Preferred Embodiment Refer now to Figure la in which latching register 1000 is shown. Register 1000 is comprised of AND-gates 100 and 200 with their output signals S' and S'' respectively connected by lines 150 and 250 respectively to input terminals of OR-gate 300. The output signal S from OR-gate 300 is provided over line 350 and is also used as a feedback signal F to AND-gate 200. AND-gate 200 also receives a reset signal R and a clock signal C at its output terminals. AND-gate 100 receives a complementary clock signal C
and data signals A and B at its input terminals. It is noted that-although two data input signals A ancl B are used in the present embodlment, this is merely illustrative and a different number of data input signals could be used as clescrlbed below.
Referring now to ~igure lb, a circuit d~agram for implemen-ting register 1000 is shown. Identical letters and numbers in the drawings refer to identical parts and signals. Input signals A, B and C are provided over lines 105, 110 and 115~ respectively, to the bases of transistors 120, 125 and 130, respectively. Translstors .
120, 125 and 130 have commonly connected collectors coupled to ground and commonly connected emitters coupled through Rl to VEE
(which in the present embodiment is -3.3 volts). This structure of commonly connected transistors with their bases responsive to dif-ferent input signals provides the input terminal structure for an AND-gate. It is noted that the design of a circuit with commonly connected collectors which performs required functions provides an essential feature of the present invention. In particular 3 this .. ~, .
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~ 5-feature allows for high density se~iconductor chips for the circuit by using well-known fabrication processes ~or semiconductor chips, as discussed infraO
A register with a different number of data input terminals may also be provided. If only a single data input signal is required (instead of two as shown in Figures la and lb), input Signal B, line llO, and transistor 125 may be deleted from the circuit.
Alternately, if additional data signals are required, additional input lines and corresponding transistors may be included in the circuit. Gate lO0 is a current mode logic gate. It is required to have a transistor for providing an alternate current path (i.e., alternate to the path through 120, 125 and/or 130) from ground through Rl to VEE. Transistor 140 provides this function with its emitter connected by Rl to VEE, its collector connected through RO to ground, and its base connected to VREF. In the present embodiment VREF is -0.26 voltsO
As stated, current must flow through transistor 140 or through at least one of transistors 120,125 and 130.
A voltage differentiator effect is achieved by these alternate current paths. If all of signals A, B and C
are low, then transistor 140 will be turned on. Current will flow ~rom ground through the path provided by resistor RO, line 150, transistor 140 and Rl to ~EE. In this manner, a voltage drop will occur across RO and the output signal corresponding to the voltage level on line 150 will be lo~
(with respect to ground). Correspondingly, if any of the input signals A, B or C is high, the base of the corresponding transistor will be high with respect to the base of transistor 140 and that transistor will therefore be turned on. Current will flow through the path provided by the appropriate one (or more) of transistors 120, 125 and 130; through resistor Rl to VEE, instead of travelling through resistor RO and transistor 140.
There will no longer be a voltage .~ , .
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.. ', :.. ' ... ,, . ' ' ',,,: ' ' ' . :''' . :, . . "' . ~ '' ~: ' . . : : . :. .. , .. : .
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drop across R0 and the output signal (or line 150) will be high.
In this manner an AND-gate is achieved.
It is noted that the negative logic conven~ion is used wherein a 0 corresponds to ground and a 1 corresponds to a negative voltage signal. The negative voltage signal must be negative with respect to VREF. In the pre~erred embodiment, the negative signal is approximately -0.5 volts.
Gate 200 is similar to gate 100. Signals C and R are sent over lines 205 and 215 respectively to the bases of transistors 220 and 225 respectively. Signal F is sent over line 250 to the base of transistor 230. Transistor 220, 225 and 230 have commonly connected collectors coupled to ground and commonly connected emitters coupled through R2 to VEE. The reference transistor 240 has its base connected to VREF, its emitter coupled through R2 to VEE and itscollector coupled through R0 to ground. Line 250 con-nec~ed to the collector of transistor 240 is the output line for gate 200. Line 250 is also connected to the base of transistor 230 such that feedback loop is provided to the g~te. Operation of the circuit is similar to gate 100 e~cept for the feedback mechanism.
In the present embodiment OR-gate 300 is considered to be comprlsed of resistor R0 coupled between ground the output line 150 of gate 100, also coupled between ground and line 250 of gate 200~
.~ .
Lines 150 and 250 are connected to line 350~ the output line of OR-gate 300 and of the register 1000 for carrying the output signal S~ It ls emphasized that this conception o~ OR-gate 300 is some-what arbitrary and unessential to the precise workingsof the circuit and is given to assist in understanding the correspondence between Figures la and lb. Other concepts for the components of OR-gate 300 are envlsioned without departing f'rom the scope of the present invention.
.
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~6636~3 ~ eferring now to Figure lc, a timing diagram for the cir~
cuit described in conjunction with Figure lb is shown. It is noted that Figure lc shows only one data input signal A, whereas Figures la and lb show two input signals, A and B. However, as described above, gate 100 is an AND-gate and its response to input signals A and B by corresponding transistors 120 and 125 is identical.
Therefore, only line A is shown in Figure lc. This line may be considered as the result of an AND between two or more input signals (noting that the negative logic convention isused).
There are four logical possibilities for the effect of the input signal onthe circuit, dependent on the previous state of the circuit. These combinations are 0 stored, 0 input; 0 stored, 1 input; 1 stored, 1 input; and 1 stored, 0 input. Referring now to Figure lc, the system is first described at tO. Clock signals C and C are always complementary. In a steady state, C is high, meaning a "0", and C is low, meaning a "1". Accordingly, current normally flows through transistor 130. Correspondingly, no current flows through transistor 140 (and resistor R0 due to transistor 140) so output signal S' or line 150 of gate 100 is high, that is a "0". Similarly since C is low, current does not flow through transistor 220. The reset signal R is normally in a low state so current does not flow through transistor 225. Therefore 9 in thi.s st,ate the controlling output to gate 200 is signal S " through feedback terminal F to transistor 230. It is assumed that at tO
the output signal S is a "0" (hlgh) and therefore current runs from ground through transistor 230 and resistor R2 to VEE Accor--.
dingly, transistor 240 is off. This is a steady state for thesystem.
Data input signal A is assumed to be a ItO". Both transis-tors 120 and 130 will therefore be on. At tl, clocks C and C shift . . .
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, to low and high respectively, which enables the new data input signal to be stored in the latching register 1000. Transistor 130 turns off in response to signal C going low. Current no longer runs through transistor 130, but continues to run through tran-sistor 120. There will be no e~fect on transistor 140 nor on output signal S'. Similarly the changing of signal C turns transistor 220 on. This will not affect transistor 240 however, which is already off due to transistor 230 being on. When sig-nals C and C return to their steady state condition at t2, transistor 130 turns "on" and transistor 220 turns off. ~o change results in any of the signals S, S' or S''.
Some ti~e between t2 and t3 it is assumed that data input signal A changes from a 0 to a 1 (that is, it goes low). It is noted that although input signal A goes low and thus transistor 120 is turned off, current still does not flow through transistor 140 due to the holding of transistor 130 on by signal C thigh).
At t3 signal C goes low and C goes high. With both A and C low, transistors 120 and 130 are both off and transistor 140 turns on.
Current flows through resistor R0 and slgnal S', and therefore also signal S, goes low. The S signal is fed back to the base of transistor 230 and turns transistor 230 off. Transistor 240 . .
would turn on, but for the C signal being high. At time t4 C
goes low, causing transistor 240 to turn on and the S'' signal to go low. Correspondingly C goes high, turning transistor 130 on and transistor 140 off. S' goes high, S " stays low and S
effectively stays low.
At t5 clock pulses C and C once again switch. However, the data input signal A is assumed to be held at a low level (with a "1" being stored, that is, S also being at a low level).
-C goes low, transistor 130 turns off and transistor 140 turns on such that S' goes low. C turns transistor 220 on causing tran-. 9 . .
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sistor 2ll0 to turn off and S " to go high. S' and S'' compen-æate such that S is held low. Similarly at t6 when C and C
switch back to their normal state, S' and S'' again switch and S is still held low.
Sometime between t~ and t7~ it is assumed that the data input signal A switches from a low to high state. When clocks C
and C shift at t7, transistor 120 is hëld on by signal A and transistor 140 does not turn on. Therefore, signal S' is held high. C turns transistor 220 on, causing transistor 240 to turn o~f and signal S'' to go high. Therefore, the output signal S
o~ register 1000 shifts to a high state. At t8 signals C and C switch back to their normal state and the system is back to the status explained corresponding to time tO.
The reset signal R has the following ef~ect. Reset signal R is assumed to be normall~ low and therefore transistor 225 is off and has no effect on the operation of the circuit. When the output signal S " of gate 200 is high, transistor 230 is on and transistor 240 is off. In such a state, the shifting of R to a high condition will cause transistor 225 to also turn on but has no af~ect on output signal S''~ s~nce transistor 240 is already off. In other wordsg the latch mechanism is not affected. How-ever, if output signal S'' of gate 200 is low (that is, transis-.
tor 2~0 is on and transistor 230 is off), then reset signal R
has an affect on the latch. Specifically, when R goes high, ,, t~ansistor 225 is turned on causing transistor 240 to turn offand signal S " to go high. The S " signal then turns transistor 230 on. When reset signal R returns to a low state, transistoor 225 turns o~f, but current still does not flow through transistor 2~0 because transistor 230 stays on due to the signal S " being high. In this manner, the reset signal R resets the latch from 10 .
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a "1" to a "0" storage state.
Referring now to Figure 2a3 latching register 2000 is shown.
It is noted again that throughout this specification identical labels are used in different drawings to denote equivalent parts.
Comparison of register 2000 with register 1000 shows that the difference between the two registers is the addition of AND-gate 400 to register 2000. AND-gate 400 receives signals from data input lines X and Y and hs an input terminal connected to clock C. The output signal from gate 400 is sent over line 450 to another input termi~al of OR-gate 300.- The functional difference between register 2000 and register 1000 is that register 2000 comprises an And/Or register. Whereas register 1000 has either a single data input signal A or two data input signals A and B
which are ANDed together for storage in latching register 10007 register 2000 has four data input signals A, B, X and Y. A and B are ANDed by AND-gate 200 as are X and Y by-AND-gate 400. The c ombination of A.B and X.Y are then ORed by OR-gate 300 such that the signal stored and generated by latching gate 2000 is the logical equivalent of A.B~X.Y.
Referring now to Figure 2b, a circult diagram for imple-menting the register 2000 of Figure 2a is shown. Comparison of Figure 2b to Figure 1~ shows that blocks 100 and 200 are identical in the two figures. However, Figure 2b has the additional block 400. Block 400 is identical to block 100 with the exception that lines 405 and 1~10 couple data input signals X and Y to transistors 420 and 425 respectively, as well as lines 105 and 110 coupllng signals A and B to transistors 120 and 125 respectively, Although a timing diagram is not given for Figure 2b, one of ordinary skill ln the art could readily understand its operation given its simi-larlty to Figure 1~, e~plained by Figure lc. Speci~ically, Figure lc shows a single data input signal A. As described above~
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the operation of the circuit shown in Figure lb is understood if line A of Figure lc is interpreted as A.B. o~ Figures la and lb. Therefore, the circuit shown in Figure 2b is understood if line A of Figure lc is interpreted as A.B.+X.Y of Figures 2a and 2b.
The design characteristics of the above discussed cir-cuits are essential features of the present invention. Specif-ically, the circuits of Figures lb and 2b have certain character-istics which should be discussed in additional detail. Each of the gates 100~ 200, 400 includes a plurality of input tr~nsistors tfor example, transistors 120, 125, 130 of gate 100) with their collectors commonly connected. This provides the feature that these transistors may be fabricated within a single "tank" or isolated region under well-known semiconductor fabrication processes.
Inclusion of several transistors within a single tank allows for high density circuits. Similarly a single resistor Rl is shared by all of the transistors in gate 100, resistor R2 is shared by all of the transistors of gate 400. An additional high-density feature is the sharing of R0 by transistors 140, 240 and 440.
Such sharing is an ess~ntial design feature which provides the functional requirements of the circuit while simultaneously en-hancing the density and power performance of the circult.
Register systems utilizing the above-discussed circuits are now presented. These register systems comprise 5 and 10-bit pa~allel storage capacity. However, in general an N-bit register is envisioned where a speci~ic value for N will be the choice of .
the system designer.
Referring now to Figure 3, a ten-bit parallel storage reglster system is shown. Basic components of Figure 3 are 10 registers Rl to R10. Each register Rl to R10 is comprised of a c~rcuit identical to Figures la and lb (with the exceptlon that the input . , .
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elements - si~nal B, line 110 and transistor 125 - are omitted from the circuit). Data input signals to registers Rl to R10 are Al to A10 respectively. The output signals for the registers are signals Sl to S10 respectiv~ly, which are fed into buffer gates Bl to B10 respectively. Buffer gates Bl to B5 are commonly enabled b~ an upper level amplified enabling signal Eu.
Lower level buffer gates B6 to Blo are commonly enabled by an amplified enabling signal EL. Outputs from gates Bl to B10 are the equivalent to signal Sl to S10 and their complements. The reset signal for registers Rl to R10 is generated by a system level signal reset gated by an inverting amplifier. In this manner, system reset pulse with its normal state being a "0" and reset state being a "1" is inverted to the requirements of regis-ters 1000 and 2000, ~iscussed above. The in~erter complements the signal R~SET of Figure 3 for the characteristics of signal R of Figures la, lb, 2a and 2b described above.
Also shown in Figure 3 is clocking circuit 360. - Clocking circuit 360 is comprised of an ampl:Lfier 370 connected to a sys-tem strobe signal STR. The positive output terminal of amplifier 370 is connected directly to an input terminal of each of gates 380 and 385. The complementary output terminal of amplifier 370 is coupled by a delay 375 to another input terminal of each of gates 380 and 385. Gates 380 and 385 will normally generate a 0 :, ` signal when the STR signal is a 0. When the STR pulse goes to a 1, gates 380 and 385 will also go to a 1 until the complementary s output signal of amplifier 370, which is delayed by delay 375, changes to a 0. In this manner, the duration of a 1 pulse corre-sponding to the C signal from gates 380 and 385 wlll be deter-mined by the time delay of delay 375. Delay 375 may simply be comprised of a plurallty of gates, each with ~ given time constant . ~
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for its response. The overall delay time for delay 375 will be the summation of the individual delays forming delay 375. Gate 380 also has an upper level control signal CNu as an input signal. It is also necessary for CNu to be at a 1 level for gate 380 to gen-erate a 1 signal and for upper level registers Rl to R5 to receive clock pulses Cu. Similarly the operation of gate 385 is enabled by lower level control pulse signal CNL. In this manner, the five upper level and five lower level bit registers can be pulsed in parallel. Alternatively, all ten of the registers Rl to R10 may be pulsed in parallel (for example~ by commonly connecting control pulses CNL to CNU). Alternative partitioning of the register system will be obvious to one of ordinary skillin the art.
Referring now to Figure 4, an alternative embodiment of the present invention is shown. Figure 4 shows a 5-bit ~nd/Or register system. Basic components of the And/Or register system are regis-ters Rll to ~15. Each of registers Rll to R15 is a circuit identical to that shown in Figures 2a and 2b with ~orresponding inputs All, Bll, Xll, Yll, etc. Output signals from registers Rll to R15 are signals Sll to S15 which have the following rela-tionship SI = AI BI+YI-YI Signals Sll to S15 are fed into bu~fer gates Bll to B15 respectively. Buffer gates Bll to B15 are enabled by the signal E appropriately amplified. The buffer gates Bll to B15 provide at their output terminals the equivalent of signals Sll to S15 and their complements. Registers Rll to R15 have a reset signal sent to them through an inverting gate as descrlbed above with respect to Figure 3. They also have common clock signals C
and ~ sent from the complementary output terminals of gate 480 of clock 460. Clock 460 is enabled by strobe signal STR and also includes gate 470 and delay 475. The operation of clock 460 is equivalent to that of clock 360 described above, except gate 480 is enabled by a signal control signal CN.
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Referring now to Figure 5, 5-bit And/Or Master/Slave register system is shown. Basic components of this register system are registers R21 to R25~ each of which is composed of a register circuit identical to that shown in Figure 2b. The register system is also comprised of registers R31 to R35, each of which is equivalent to the circuit shown in Figure lb. Regis-ters R21 to R25 provide output signals S21 to S25 respectively, which have the following relationships with respect to their input signals: SI ~ AI.BI+XI.YI. Registers R21 to R25 are re-sponsive to a reset signal sent through appropriate inverting amplifying means and are also responsive to clock 560 which is identical to clock 460. Registers R31 to R35 have output signals S31 to S35 respectively fed into buffer gates B31 to B35 respec-tively. Buffer gates B31 to B35 are commonly enabled by a suit-ably amplified enabling signal E and provide at-their output terminals the equivalent of signals S31 to S35 and their comple-ments. The data input signals for registers R31 to R 35 are the output signals S21 to S25 from registers R21 to R25. Clock signals for registers R31 to R35 are also provided by clock 560. However, it is noted that whereas registers R21 to R25 have clock signals C and C such that the C signal is fed into the AND-gates 100, 400 and the C signal is fed into the reset gate 200, registers R31 to R35 have signal C fed into their reset gates 200 and the signal C is ~ed into their data input gates 100. This inverted pulse gener-ation æcheme provides an essential feature of the present invention.
The master /slave regster shown in Figure 5 provides a , ~;
delay between storing the input signals to registers R21 to ~25 and providing output signals from buffers B31 to B35. This is a requirement for providing a register which can be used as a com-ponent in a serial shift register as explained with reference to ` Figure 6. Referring now to Figure 6, a 3-bit serial (or shift) ` 15.
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register is shown. This serial register is comprlsed of indiv-idual bit registers 60, 70 and 80. Bits 60, 70 and 80 are enabled by clock signals CL and have input and output terminals 61 and 62, 71 and 72, 81 and 82 respectively. The input data signal DIN to the shift register is sent to terminal 61 and the output signal DoUT from the 3-bit shift register is sent from terminal 82. The timing problem presented by the 3-bit shift register of Figure 6 (which is typical of an N-bit shift register) is as follows: Clock signals enable a change in the data stored in each of cells 60, 70, 80. The data DIN present at an input terminal 61 will be stored in cell 60 during each cycle. It is desired to transfer data from cell 60 to cell 70, from cell 70 to cell 80 and from cell 80 out as signal DQUT during each cycle.
To accomplish this, the old data stored in cells 60, 70, 80 (i.e.
the data stored during the previous cycle) must be present and held at output terminals 62, 72, 82 for transmission to cell 70, 80 and outward during each cycle. If the output from cell 60 changes before cell 70 "latches" the data from the previous cycle, the data DIN will be stored in cell 70 as well as cell 60 and the old data stored in cell 60 will be lost. The same problem is posed between cells 70 and 80 as well as any two consecukive cells in a shift register. In other words a shift register simply com-prised of registers such as register 1000 or 2000 described above, would not function properly due to timing problems. It is required, therefore, to separate the output state of each cell of khe shift register from the input stage, and to hold the output stage at a state corresponding to the previous cycle for a duration suffic1ent to allow a latching of the old data in the successive cell.
~ eferring once again to Figure 5, the Master/Slave reglster system comprised of a combination of registers 1000 and 2000 with a pulse generating eystem solves this timing problem. Speci~i-: - .
.~ . .
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~636~
cally, input signals A21 to A25 are stored in registers R21 to R25, respectively, upon the presence of appropriate strobe STR
and control CN signals. At the same time, the data previously stored in registers R21 to R25 (which is the same as that stored in registers R31 to R35), is transferred through buffer gates B31 to B35 to the next register cell. However, when the ~trobe STR and control CN signals cause clock signals C and ~ to enable input data to be stored ln registers R21 to R25, data is not immediately transferred from R21-R25 to R31-R35. Specifically, due to the inverse timing of R31-35 with respect to the timing of R21-R35 (that is~ due to their enabling by C and C as opposed to C and C) there is a delay between the storage of the input signals in registers R31 to R35. In this manner, although signals S21 to S25 change to the new input levels, the output signals S31 to S35 are held at levels corresponding to the previous cycle until C and C switch back to their normal levels. Accordingly, the amount of time required for the delay in the pulse shape of ~..
C and C is go~erned by internal swikching characteristics of the gates, both to store data as well as to propagate data. When C
and C switch from high to low and low to high, respectively, data is stored in master cells R21 to R25 and slave cells R31 to R35, which act as gates holding the values from the previous cycle. When C and C switch back to high and low respectively, cells R21 to R25 latch in their new values and cells R31 to R35 switch values to correspond to the new input values.
While the principles of the present invention have now been descrlbed with respect to the illustrated embodiments discussed above, there will be obvious to those skilled in the art many modifications in structural arrangement and components used in the practice of the invention without departing from the above-enumer-.
17.
~66369 ated principles. For example~ although the transistor elements shown inthe drawings demonstrate the invention with NPN type components it will be clear that PNP type transistor elements can be used with appropriate refer-ence potentials and logic convention.
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back gate.
One embodiment of the latch includes a single data input gate and a latching gate and stores either a single data input or the AND function of several data input signals. An alternative embodiment of the latch includes a plurality of data input gates and a single latching gate and performs an AND/OR function on a plurality of data input signals prior to storing the result.
These embodiments of the latch may be combined to form register systems. One combination of the latching register circuit provides the basic components (i.e. bit cells) for a shift register. This shift register includes a simple clocking system which provides a built-in delay mechanism for proper operation of the shift register.
Thus, according to a broad aspect of the present invention, there - is provided a current mode logic circuit responsive to complementary first and second clock signals for storing a logical AND function of a plurality of input signals, said circuit comprising: firstJ second and third reference voltage means, each of said reference voltage means producing a first, second and third voltage signal, said seconcl voltage signal of a level between said first and said third voltage signals; a first transistor with its base -. ~
coupled to said second reference voltage means; a second transistor with its base connected to recèive said first clock signals; a plurality of other transistors, each of sald other transistors having its base connected to receive one of said plurality of input signals, the collectors of said second ~ -and said other transistors commonly connected to said first reference voltage means; first resistive means commonly connecting the emitters of said first, second and other transistors to said third reference voltage means; a third transistor with its base connected to said second reference voltage means;
~, a fourth transistor with its base connected to receive said second clock signals; a fifth transistor with its base connected to the collector of said third t-ransistor, the collectors of said fourth and fifth transistors common-ly connected to said first reference voltage means; second resistive means commonly connecting the emit~ers of said third, fourth and fifth transistors ~ -4-.~,,~
~663~
to said third reference voltage means; and third resistive means coupling the collectors of said first and said third transistors to said first reference voltage means.
The invention will now be described in greater detail with refer- :
ence to the accompanying drawings, in which:
Figure la is a logic diagram of the basic latching register of the . present invention;
Figure lb is a circuit diagram for implementing the latching register shown in Figure la;
Figure lc is a timing diagram which explains the operation of the .:.
circuit shown in Figure lb;
Figure 2a is a logic diagram of an AND/~R latching register of the present invention;
. Figure 2b is a circuit diagram for implementing the AND./OR latching register shown in Figure 2c;
.` Figure 3 is a block diagram of a ten-bit parallel storage register . system, an embodiment of the present invention;
`~ Figure 4 is a block diagram of a five-bit AND/OR parallel register sys~em, an embodiment of the present invention;
Figure S is a block diagram of a five-bit ~NDlOR Master~Slave .;~ . .
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parallel register system, an embodiment of the present invention, and Figure 6 is a block diagram of a three-bit shift register.
Description of a Preferred Embodiment Refer now to Figure la in which latching register 1000 is shown. Register 1000 is comprised of AND-gates 100 and 200 with their output signals S' and S'' respectively connected by lines 150 and 250 respectively to input terminals of OR-gate 300. The output signal S from OR-gate 300 is provided over line 350 and is also used as a feedback signal F to AND-gate 200. AND-gate 200 also receives a reset signal R and a clock signal C at its output terminals. AND-gate 100 receives a complementary clock signal C
and data signals A and B at its input terminals. It is noted that-although two data input signals A ancl B are used in the present embodlment, this is merely illustrative and a different number of data input signals could be used as clescrlbed below.
Referring now to ~igure lb, a circuit d~agram for implemen-ting register 1000 is shown. Identical letters and numbers in the drawings refer to identical parts and signals. Input signals A, B and C are provided over lines 105, 110 and 115~ respectively, to the bases of transistors 120, 125 and 130, respectively. Translstors .
120, 125 and 130 have commonly connected collectors coupled to ground and commonly connected emitters coupled through Rl to VEE
(which in the present embodiment is -3.3 volts). This structure of commonly connected transistors with their bases responsive to dif-ferent input signals provides the input terminal structure for an AND-gate. It is noted that the design of a circuit with commonly connected collectors which performs required functions provides an essential feature of the present invention. In particular 3 this .. ~, .
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~ 5-feature allows for high density se~iconductor chips for the circuit by using well-known fabrication processes ~or semiconductor chips, as discussed infraO
A register with a different number of data input terminals may also be provided. If only a single data input signal is required (instead of two as shown in Figures la and lb), input Signal B, line llO, and transistor 125 may be deleted from the circuit.
Alternately, if additional data signals are required, additional input lines and corresponding transistors may be included in the circuit. Gate lO0 is a current mode logic gate. It is required to have a transistor for providing an alternate current path (i.e., alternate to the path through 120, 125 and/or 130) from ground through Rl to VEE. Transistor 140 provides this function with its emitter connected by Rl to VEE, its collector connected through RO to ground, and its base connected to VREF. In the present embodiment VREF is -0.26 voltsO
As stated, current must flow through transistor 140 or through at least one of transistors 120,125 and 130.
A voltage differentiator effect is achieved by these alternate current paths. If all of signals A, B and C
are low, then transistor 140 will be turned on. Current will flow ~rom ground through the path provided by resistor RO, line 150, transistor 140 and Rl to ~EE. In this manner, a voltage drop will occur across RO and the output signal corresponding to the voltage level on line 150 will be lo~
(with respect to ground). Correspondingly, if any of the input signals A, B or C is high, the base of the corresponding transistor will be high with respect to the base of transistor 140 and that transistor will therefore be turned on. Current will flow through the path provided by the appropriate one (or more) of transistors 120, 125 and 130; through resistor Rl to VEE, instead of travelling through resistor RO and transistor 140.
There will no longer be a voltage .~ , .
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drop across R0 and the output signal (or line 150) will be high.
In this manner an AND-gate is achieved.
It is noted that the negative logic conven~ion is used wherein a 0 corresponds to ground and a 1 corresponds to a negative voltage signal. The negative voltage signal must be negative with respect to VREF. In the pre~erred embodiment, the negative signal is approximately -0.5 volts.
Gate 200 is similar to gate 100. Signals C and R are sent over lines 205 and 215 respectively to the bases of transistors 220 and 225 respectively. Signal F is sent over line 250 to the base of transistor 230. Transistor 220, 225 and 230 have commonly connected collectors coupled to ground and commonly connected emitters coupled through R2 to VEE. The reference transistor 240 has its base connected to VREF, its emitter coupled through R2 to VEE and itscollector coupled through R0 to ground. Line 250 con-nec~ed to the collector of transistor 240 is the output line for gate 200. Line 250 is also connected to the base of transistor 230 such that feedback loop is provided to the g~te. Operation of the circuit is similar to gate 100 e~cept for the feedback mechanism.
In the present embodiment OR-gate 300 is considered to be comprlsed of resistor R0 coupled between ground the output line 150 of gate 100, also coupled between ground and line 250 of gate 200~
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Lines 150 and 250 are connected to line 350~ the output line of OR-gate 300 and of the register 1000 for carrying the output signal S~ It ls emphasized that this conception o~ OR-gate 300 is some-what arbitrary and unessential to the precise workingsof the circuit and is given to assist in understanding the correspondence between Figures la and lb. Other concepts for the components of OR-gate 300 are envlsioned without departing f'rom the scope of the present invention.
.
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~6636~3 ~ eferring now to Figure lc, a timing diagram for the cir~
cuit described in conjunction with Figure lb is shown. It is noted that Figure lc shows only one data input signal A, whereas Figures la and lb show two input signals, A and B. However, as described above, gate 100 is an AND-gate and its response to input signals A and B by corresponding transistors 120 and 125 is identical.
Therefore, only line A is shown in Figure lc. This line may be considered as the result of an AND between two or more input signals (noting that the negative logic convention isused).
There are four logical possibilities for the effect of the input signal onthe circuit, dependent on the previous state of the circuit. These combinations are 0 stored, 0 input; 0 stored, 1 input; 1 stored, 1 input; and 1 stored, 0 input. Referring now to Figure lc, the system is first described at tO. Clock signals C and C are always complementary. In a steady state, C is high, meaning a "0", and C is low, meaning a "1". Accordingly, current normally flows through transistor 130. Correspondingly, no current flows through transistor 140 (and resistor R0 due to transistor 140) so output signal S' or line 150 of gate 100 is high, that is a "0". Similarly since C is low, current does not flow through transistor 220. The reset signal R is normally in a low state so current does not flow through transistor 225. Therefore 9 in thi.s st,ate the controlling output to gate 200 is signal S " through feedback terminal F to transistor 230. It is assumed that at tO
the output signal S is a "0" (hlgh) and therefore current runs from ground through transistor 230 and resistor R2 to VEE Accor--.
dingly, transistor 240 is off. This is a steady state for thesystem.
Data input signal A is assumed to be a ItO". Both transis-tors 120 and 130 will therefore be on. At tl, clocks C and C shift . . .
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, to low and high respectively, which enables the new data input signal to be stored in the latching register 1000. Transistor 130 turns off in response to signal C going low. Current no longer runs through transistor 130, but continues to run through tran-sistor 120. There will be no e~fect on transistor 140 nor on output signal S'. Similarly the changing of signal C turns transistor 220 on. This will not affect transistor 240 however, which is already off due to transistor 230 being on. When sig-nals C and C return to their steady state condition at t2, transistor 130 turns "on" and transistor 220 turns off. ~o change results in any of the signals S, S' or S''.
Some ti~e between t2 and t3 it is assumed that data input signal A changes from a 0 to a 1 (that is, it goes low). It is noted that although input signal A goes low and thus transistor 120 is turned off, current still does not flow through transistor 140 due to the holding of transistor 130 on by signal C thigh).
At t3 signal C goes low and C goes high. With both A and C low, transistors 120 and 130 are both off and transistor 140 turns on.
Current flows through resistor R0 and slgnal S', and therefore also signal S, goes low. The S signal is fed back to the base of transistor 230 and turns transistor 230 off. Transistor 240 . .
would turn on, but for the C signal being high. At time t4 C
goes low, causing transistor 240 to turn on and the S'' signal to go low. Correspondingly C goes high, turning transistor 130 on and transistor 140 off. S' goes high, S " stays low and S
effectively stays low.
At t5 clock pulses C and C once again switch. However, the data input signal A is assumed to be held at a low level (with a "1" being stored, that is, S also being at a low level).
-C goes low, transistor 130 turns off and transistor 140 turns on such that S' goes low. C turns transistor 220 on causing tran-. 9 . .
~6!63~
sistor 2ll0 to turn off and S " to go high. S' and S'' compen-æate such that S is held low. Similarly at t6 when C and C
switch back to their normal state, S' and S'' again switch and S is still held low.
Sometime between t~ and t7~ it is assumed that the data input signal A switches from a low to high state. When clocks C
and C shift at t7, transistor 120 is hëld on by signal A and transistor 140 does not turn on. Therefore, signal S' is held high. C turns transistor 220 on, causing transistor 240 to turn o~f and signal S'' to go high. Therefore, the output signal S
o~ register 1000 shifts to a high state. At t8 signals C and C switch back to their normal state and the system is back to the status explained corresponding to time tO.
The reset signal R has the following ef~ect. Reset signal R is assumed to be normall~ low and therefore transistor 225 is off and has no effect on the operation of the circuit. When the output signal S " of gate 200 is high, transistor 230 is on and transistor 240 is off. In such a state, the shifting of R to a high condition will cause transistor 225 to also turn on but has no af~ect on output signal S''~ s~nce transistor 240 is already off. In other wordsg the latch mechanism is not affected. How-ever, if output signal S'' of gate 200 is low (that is, transis-.
tor 2~0 is on and transistor 230 is off), then reset signal R
has an affect on the latch. Specifically, when R goes high, ,, t~ansistor 225 is turned on causing transistor 240 to turn offand signal S " to go high. The S " signal then turns transistor 230 on. When reset signal R returns to a low state, transistoor 225 turns o~f, but current still does not flow through transistor 2~0 because transistor 230 stays on due to the signal S " being high. In this manner, the reset signal R resets the latch from 10 .
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a "1" to a "0" storage state.
Referring now to Figure 2a3 latching register 2000 is shown.
It is noted again that throughout this specification identical labels are used in different drawings to denote equivalent parts.
Comparison of register 2000 with register 1000 shows that the difference between the two registers is the addition of AND-gate 400 to register 2000. AND-gate 400 receives signals from data input lines X and Y and hs an input terminal connected to clock C. The output signal from gate 400 is sent over line 450 to another input termi~al of OR-gate 300.- The functional difference between register 2000 and register 1000 is that register 2000 comprises an And/Or register. Whereas register 1000 has either a single data input signal A or two data input signals A and B
which are ANDed together for storage in latching register 10007 register 2000 has four data input signals A, B, X and Y. A and B are ANDed by AND-gate 200 as are X and Y by-AND-gate 400. The c ombination of A.B and X.Y are then ORed by OR-gate 300 such that the signal stored and generated by latching gate 2000 is the logical equivalent of A.B~X.Y.
Referring now to Figure 2b, a circult diagram for imple-menting the register 2000 of Figure 2a is shown. Comparison of Figure 2b to Figure 1~ shows that blocks 100 and 200 are identical in the two figures. However, Figure 2b has the additional block 400. Block 400 is identical to block 100 with the exception that lines 405 and 1~10 couple data input signals X and Y to transistors 420 and 425 respectively, as well as lines 105 and 110 coupllng signals A and B to transistors 120 and 125 respectively, Although a timing diagram is not given for Figure 2b, one of ordinary skill ln the art could readily understand its operation given its simi-larlty to Figure 1~, e~plained by Figure lc. Speci~ically, Figure lc shows a single data input signal A. As described above~
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~6~6~369~
the operation of the circuit shown in Figure lb is understood if line A of Figure lc is interpreted as A.B. o~ Figures la and lb. Therefore, the circuit shown in Figure 2b is understood if line A of Figure lc is interpreted as A.B.+X.Y of Figures 2a and 2b.
The design characteristics of the above discussed cir-cuits are essential features of the present invention. Specif-ically, the circuits of Figures lb and 2b have certain character-istics which should be discussed in additional detail. Each of the gates 100~ 200, 400 includes a plurality of input tr~nsistors tfor example, transistors 120, 125, 130 of gate 100) with their collectors commonly connected. This provides the feature that these transistors may be fabricated within a single "tank" or isolated region under well-known semiconductor fabrication processes.
Inclusion of several transistors within a single tank allows for high density circuits. Similarly a single resistor Rl is shared by all of the transistors in gate 100, resistor R2 is shared by all of the transistors of gate 400. An additional high-density feature is the sharing of R0 by transistors 140, 240 and 440.
Such sharing is an ess~ntial design feature which provides the functional requirements of the circuit while simultaneously en-hancing the density and power performance of the circult.
Register systems utilizing the above-discussed circuits are now presented. These register systems comprise 5 and 10-bit pa~allel storage capacity. However, in general an N-bit register is envisioned where a speci~ic value for N will be the choice of .
the system designer.
Referring now to Figure 3, a ten-bit parallel storage reglster system is shown. Basic components of Figure 3 are 10 registers Rl to R10. Each register Rl to R10 is comprised of a c~rcuit identical to Figures la and lb (with the exceptlon that the input . , .
12.
~L~663~
elements - si~nal B, line 110 and transistor 125 - are omitted from the circuit). Data input signals to registers Rl to R10 are Al to A10 respectively. The output signals for the registers are signals Sl to S10 respectiv~ly, which are fed into buffer gates Bl to B10 respectively. Buffer gates Bl to B5 are commonly enabled b~ an upper level amplified enabling signal Eu.
Lower level buffer gates B6 to Blo are commonly enabled by an amplified enabling signal EL. Outputs from gates Bl to B10 are the equivalent to signal Sl to S10 and their complements. The reset signal for registers Rl to R10 is generated by a system level signal reset gated by an inverting amplifier. In this manner, system reset pulse with its normal state being a "0" and reset state being a "1" is inverted to the requirements of regis-ters 1000 and 2000, ~iscussed above. The in~erter complements the signal R~SET of Figure 3 for the characteristics of signal R of Figures la, lb, 2a and 2b described above.
Also shown in Figure 3 is clocking circuit 360. - Clocking circuit 360 is comprised of an ampl:Lfier 370 connected to a sys-tem strobe signal STR. The positive output terminal of amplifier 370 is connected directly to an input terminal of each of gates 380 and 385. The complementary output terminal of amplifier 370 is coupled by a delay 375 to another input terminal of each of gates 380 and 385. Gates 380 and 385 will normally generate a 0 :, ` signal when the STR signal is a 0. When the STR pulse goes to a 1, gates 380 and 385 will also go to a 1 until the complementary s output signal of amplifier 370, which is delayed by delay 375, changes to a 0. In this manner, the duration of a 1 pulse corre-sponding to the C signal from gates 380 and 385 wlll be deter-mined by the time delay of delay 375. Delay 375 may simply be comprised of a plurallty of gates, each with ~ given time constant . ~
13.
~663~i~
for its response. The overall delay time for delay 375 will be the summation of the individual delays forming delay 375. Gate 380 also has an upper level control signal CNu as an input signal. It is also necessary for CNu to be at a 1 level for gate 380 to gen-erate a 1 signal and for upper level registers Rl to R5 to receive clock pulses Cu. Similarly the operation of gate 385 is enabled by lower level control pulse signal CNL. In this manner, the five upper level and five lower level bit registers can be pulsed in parallel. Alternatively, all ten of the registers Rl to R10 may be pulsed in parallel (for example~ by commonly connecting control pulses CNL to CNU). Alternative partitioning of the register system will be obvious to one of ordinary skillin the art.
Referring now to Figure 4, an alternative embodiment of the present invention is shown. Figure 4 shows a 5-bit ~nd/Or register system. Basic components of the And/Or register system are regis-ters Rll to ~15. Each of registers Rll to R15 is a circuit identical to that shown in Figures 2a and 2b with ~orresponding inputs All, Bll, Xll, Yll, etc. Output signals from registers Rll to R15 are signals Sll to S15 which have the following rela-tionship SI = AI BI+YI-YI Signals Sll to S15 are fed into bu~fer gates Bll to B15 respectively. Buffer gates Bll to B15 are enabled by the signal E appropriately amplified. The buffer gates Bll to B15 provide at their output terminals the equivalent of signals Sll to S15 and their complements. Registers Rll to R15 have a reset signal sent to them through an inverting gate as descrlbed above with respect to Figure 3. They also have common clock signals C
and ~ sent from the complementary output terminals of gate 480 of clock 460. Clock 460 is enabled by strobe signal STR and also includes gate 470 and delay 475. The operation of clock 460 is equivalent to that of clock 360 described above, except gate 480 is enabled by a signal control signal CN.
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Referring now to Figure 5, 5-bit And/Or Master/Slave register system is shown. Basic components of this register system are registers R21 to R25~ each of which is composed of a register circuit identical to that shown in Figure 2b. The register system is also comprised of registers R31 to R35, each of which is equivalent to the circuit shown in Figure lb. Regis-ters R21 to R25 provide output signals S21 to S25 respectively, which have the following relationships with respect to their input signals: SI ~ AI.BI+XI.YI. Registers R21 to R25 are re-sponsive to a reset signal sent through appropriate inverting amplifying means and are also responsive to clock 560 which is identical to clock 460. Registers R31 to R35 have output signals S31 to S35 respectively fed into buffer gates B31 to B35 respec-tively. Buffer gates B31 to B35 are commonly enabled by a suit-ably amplified enabling signal E and provide at-their output terminals the equivalent of signals S31 to S35 and their comple-ments. The data input signals for registers R31 to R 35 are the output signals S21 to S25 from registers R21 to R25. Clock signals for registers R31 to R35 are also provided by clock 560. However, it is noted that whereas registers R21 to R25 have clock signals C and C such that the C signal is fed into the AND-gates 100, 400 and the C signal is fed into the reset gate 200, registers R31 to R35 have signal C fed into their reset gates 200 and the signal C is ~ed into their data input gates 100. This inverted pulse gener-ation æcheme provides an essential feature of the present invention.
The master /slave regster shown in Figure 5 provides a , ~;
delay between storing the input signals to registers R21 to ~25 and providing output signals from buffers B31 to B35. This is a requirement for providing a register which can be used as a com-ponent in a serial shift register as explained with reference to ` Figure 6. Referring now to Figure 6, a 3-bit serial (or shift) ` 15.
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6636~
register is shown. This serial register is comprlsed of indiv-idual bit registers 60, 70 and 80. Bits 60, 70 and 80 are enabled by clock signals CL and have input and output terminals 61 and 62, 71 and 72, 81 and 82 respectively. The input data signal DIN to the shift register is sent to terminal 61 and the output signal DoUT from the 3-bit shift register is sent from terminal 82. The timing problem presented by the 3-bit shift register of Figure 6 (which is typical of an N-bit shift register) is as follows: Clock signals enable a change in the data stored in each of cells 60, 70, 80. The data DIN present at an input terminal 61 will be stored in cell 60 during each cycle. It is desired to transfer data from cell 60 to cell 70, from cell 70 to cell 80 and from cell 80 out as signal DQUT during each cycle.
To accomplish this, the old data stored in cells 60, 70, 80 (i.e.
the data stored during the previous cycle) must be present and held at output terminals 62, 72, 82 for transmission to cell 70, 80 and outward during each cycle. If the output from cell 60 changes before cell 70 "latches" the data from the previous cycle, the data DIN will be stored in cell 70 as well as cell 60 and the old data stored in cell 60 will be lost. The same problem is posed between cells 70 and 80 as well as any two consecukive cells in a shift register. In other words a shift register simply com-prised of registers such as register 1000 or 2000 described above, would not function properly due to timing problems. It is required, therefore, to separate the output state of each cell of khe shift register from the input stage, and to hold the output stage at a state corresponding to the previous cycle for a duration suffic1ent to allow a latching of the old data in the successive cell.
~ eferring once again to Figure 5, the Master/Slave reglster system comprised of a combination of registers 1000 and 2000 with a pulse generating eystem solves this timing problem. Speci~i-: - .
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cally, input signals A21 to A25 are stored in registers R21 to R25, respectively, upon the presence of appropriate strobe STR
and control CN signals. At the same time, the data previously stored in registers R21 to R25 (which is the same as that stored in registers R31 to R35), is transferred through buffer gates B31 to B35 to the next register cell. However, when the ~trobe STR and control CN signals cause clock signals C and ~ to enable input data to be stored ln registers R21 to R25, data is not immediately transferred from R21-R25 to R31-R35. Specifically, due to the inverse timing of R31-35 with respect to the timing of R21-R35 (that is~ due to their enabling by C and C as opposed to C and C) there is a delay between the storage of the input signals in registers R31 to R35. In this manner, although signals S21 to S25 change to the new input levels, the output signals S31 to S35 are held at levels corresponding to the previous cycle until C and C switch back to their normal levels. Accordingly, the amount of time required for the delay in the pulse shape of ~..
C and C is go~erned by internal swikching characteristics of the gates, both to store data as well as to propagate data. When C
and C switch from high to low and low to high, respectively, data is stored in master cells R21 to R25 and slave cells R31 to R35, which act as gates holding the values from the previous cycle. When C and C switch back to high and low respectively, cells R21 to R25 latch in their new values and cells R31 to R35 switch values to correspond to the new input values.
While the principles of the present invention have now been descrlbed with respect to the illustrated embodiments discussed above, there will be obvious to those skilled in the art many modifications in structural arrangement and components used in the practice of the invention without departing from the above-enumer-.
17.
~66369 ated principles. For example~ although the transistor elements shown inthe drawings demonstrate the invention with NPN type components it will be clear that PNP type transistor elements can be used with appropriate refer-ence potentials and logic convention.
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Claims (10)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A current mode logic circuit responsive to complementary first and second clock signals for storing a logical AND function of a plurality of input signals, said circuit comprising:
first, second and third reference voltage means, each of said reference voltage means producing a first, second and third voltage signal, said second voltage signal of a level between said first and said third voltage signals;
a first transistor with its base coupled to said second refer-ence voltage means;
a second transistor with its base connected to receive said first clock signals;
a plurality of other transistors" each of said other transistors having its base connected to receive one of said plurality of input signals, the collectors of said second and said other transistors commonly connected to said first reference voltage means;
first resistive means commonly connecting the emitters of said first, second and other transistors to said third reference voltage means;
a third transistor with its base connected to said second reference voltage means;
a fourth transistor with its base connected to receive said second clock signals;
a fifth transistor with its base connected to the collector of said third transistor, the collectors of said fourth and fifth transistors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth and fifth transistors to said third reference voltage means; and third resistive means coupling the collectors of said first and said third transistors to said first reference voltage means.
first, second and third reference voltage means, each of said reference voltage means producing a first, second and third voltage signal, said second voltage signal of a level between said first and said third voltage signals;
a first transistor with its base coupled to said second refer-ence voltage means;
a second transistor with its base connected to receive said first clock signals;
a plurality of other transistors" each of said other transistors having its base connected to receive one of said plurality of input signals, the collectors of said second and said other transistors commonly connected to said first reference voltage means;
first resistive means commonly connecting the emitters of said first, second and other transistors to said third reference voltage means;
a third transistor with its base connected to said second reference voltage means;
a fourth transistor with its base connected to receive said second clock signals;
a fifth transistor with its base connected to the collector of said third transistor, the collectors of said fourth and fifth transistors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth and fifth transistors to said third reference voltage means; and third resistive means coupling the collectors of said first and said third transistors to said first reference voltage means.
Claim 2 - The circuit as claimed in Claim 1 further comprising:
a sixth transistor with its base responsive to a reset signal, its collector connected to said. first reference voltage means, and its emitter connected by said second resistive means to said third reference voltage means.
a sixth transistor with its base responsive to a reset signal, its collector connected to said. first reference voltage means, and its emitter connected by said second resistive means to said third reference voltage means.
Claim 3 - A current mode logic circuit responsive to complementary first and second clock signals for storing a logical function of a plurality of input signals, said circuit comprising:
first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage signal of a level between said first and said second voltage signals;
a first transistor with its base coupled to said second reference voltage means;
a second transistor with its base connected to receive s id first clock signals;
a first plurality of other transistors, each of said first plurality of other transistors having its base connected to receive one of a first group of said plurality of input signals, the collectors of said first plurality of other transistors commonly connected to said first reference voltage means;
first resistive means commonly connecting the emitters of said first, second and first plurality of other transistors to said third refer-ence voltage means;
a third transistor with its base coupled to said second reference voltage means;
a fourth transistor with its base connected to receive said first clock signals;
a second plurality of other transistors, each of said second plurality of other transistors having its base connected to receive one of a second group of said plurality of input signals, the collectors of said second plurality of other transistors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth, and second plurality of other transistors to said third reference voltage means;
a fifth transistor with its base connected to said second refer-ence voltage means;
a sixth transistor with its base connected to receive said second clock signals;
a seventh transistor with its base connected to the collector of said fifth transistor, the collectors of said sixth and seventh transistors commonly connected to said first reference voltage means;
third resistive means commonly connecting the emitters of said fifth, sixth and seventh transistors to said third reference voltage means;
and fourth resistive means coupling the collectors of said first, said third and said fifth transistors to said first reference voltage means.
first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage signal of a level between said first and said second voltage signals;
a first transistor with its base coupled to said second reference voltage means;
a second transistor with its base connected to receive s id first clock signals;
a first plurality of other transistors, each of said first plurality of other transistors having its base connected to receive one of a first group of said plurality of input signals, the collectors of said first plurality of other transistors commonly connected to said first reference voltage means;
first resistive means commonly connecting the emitters of said first, second and first plurality of other transistors to said third refer-ence voltage means;
a third transistor with its base coupled to said second reference voltage means;
a fourth transistor with its base connected to receive said first clock signals;
a second plurality of other transistors, each of said second plurality of other transistors having its base connected to receive one of a second group of said plurality of input signals, the collectors of said second plurality of other transistors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth, and second plurality of other transistors to said third reference voltage means;
a fifth transistor with its base connected to said second refer-ence voltage means;
a sixth transistor with its base connected to receive said second clock signals;
a seventh transistor with its base connected to the collector of said fifth transistor, the collectors of said sixth and seventh transistors commonly connected to said first reference voltage means;
third resistive means commonly connecting the emitters of said fifth, sixth and seventh transistors to said third reference voltage means;
and fourth resistive means coupling the collectors of said first, said third and said fifth transistors to said first reference voltage means.
Claim 4 - The circuit as claimed in Claim 3 further comprising:
an eighth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said third resistive means to said third reference voltage means.
an eighth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said third resistive means to said third reference voltage means.
Claim 5 - A current mode logic register system comprising:
a clock circuit for generating complementary first and second clock signals having a pulse width of fixed duration; and first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage signal of a level between said first and said third voltage signals; and a plurality of parallel storage means responsive to said first and said second clock signals and each connected to receive at least one input signals each of said storage means performing a logical AND operation on said input signals and storing the result of said logical AND operation, each of said storage means comprising:
a first transistor with its base coupled to said second reference voltage means;
a second transistor with its base connected to receive said first clock signals;
a plurality of other transistors, each of said other tran-sistors, having its base connected to receive one of said input signals, the collectors of said second and said other transistors commonly connected to said first reference voltage means;
first resistive means commonly connecting the emitters of said first, second and other transistors to said third reference voltage means;
a third transistor with its base connected to said second reference voltage means;
a fourth transistor with its base connected to receive said second clock signals;
a fifth transistor with its base connected to the collector of said third transistor, the collectors of said fourth and fifth transistors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth and fifth transistors to said third reference voltage means; and third resistive means coupling the collectors of said first and said third transistors to said first reference voltage means.
a clock circuit for generating complementary first and second clock signals having a pulse width of fixed duration; and first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage signal of a level between said first and said third voltage signals; and a plurality of parallel storage means responsive to said first and said second clock signals and each connected to receive at least one input signals each of said storage means performing a logical AND operation on said input signals and storing the result of said logical AND operation, each of said storage means comprising:
a first transistor with its base coupled to said second reference voltage means;
a second transistor with its base connected to receive said first clock signals;
a plurality of other transistors, each of said other tran-sistors, having its base connected to receive one of said input signals, the collectors of said second and said other transistors commonly connected to said first reference voltage means;
first resistive means commonly connecting the emitters of said first, second and other transistors to said third reference voltage means;
a third transistor with its base connected to said second reference voltage means;
a fourth transistor with its base connected to receive said second clock signals;
a fifth transistor with its base connected to the collector of said third transistor, the collectors of said fourth and fifth transistors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth and fifth transistors to said third reference voltage means; and third resistive means coupling the collectors of said first and said third transistors to said first reference voltage means.
Claim 6 - A circuit as claimed in Claim 5 wherein each of said storage means further comprises:
a sixth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said third resistive means to said third reference voltage means.
a sixth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said third resistive means to said third reference voltage means.
Claim 7 - A current mode logic register system comprising:
a clock circuit for generating complementary first and second clock signals having a pulse width of fixed duration;
first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage sig-nal of a level between said first and said second voltage signals;
and a plurality of parallel storage means responsive to said first and said second clock signals and each connected to receive a plurality of input signals, each of said storage means performing a logical operation on said input signals and storing the result of said logical operation, each of said storage means comprising:
a first transistor with its base connected to said second reference voltage means;
a second transistor with its base connected to receive said first clock signals;
a first plurality of other transistors, each of said first plurality of other transistors having its base con-nected to receive one of a first group of said plurality of input signals, the collectors of said first plurality of other transis-tors commonly connected to said first reference voltage means;
a first resistive means commonly connecting the emitters of said first, second and first plurality of other transistors to said third reference voltage means;
a third transistor with its base coupled to said second reference voltage means;
a fourth transistor with its base connected to receive said first clock signals;
a second plurality of other transistors, each of said second plurality of other transistors having its base con-nected to receive one of a second group of said plurality of input signals, the collectors of said second plurality of other transis-tors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth, and second plurality of other transistors to said third reference voltage means;
24.
a fifth transistor with its base connected to said second reference voltage means;
a sixth transistor with its base connected to receive said second clock signals;
a seventh transistor with its base connected to the collector of said fifth transistor, the collectors of said sixth and seventh transistors commonly connected to said first reference voltage means;
third resistive means commonly connecting the emitters of said fifth, sixth and seventh transistors to said third reference voltage means; and fourth resistive means coupling the collectors of said first, said third and said fifth transistors to said first reference voltage means.
a clock circuit for generating complementary first and second clock signals having a pulse width of fixed duration;
first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage sig-nal of a level between said first and said second voltage signals;
and a plurality of parallel storage means responsive to said first and said second clock signals and each connected to receive a plurality of input signals, each of said storage means performing a logical operation on said input signals and storing the result of said logical operation, each of said storage means comprising:
a first transistor with its base connected to said second reference voltage means;
a second transistor with its base connected to receive said first clock signals;
a first plurality of other transistors, each of said first plurality of other transistors having its base con-nected to receive one of a first group of said plurality of input signals, the collectors of said first plurality of other transis-tors commonly connected to said first reference voltage means;
a first resistive means commonly connecting the emitters of said first, second and first plurality of other transistors to said third reference voltage means;
a third transistor with its base coupled to said second reference voltage means;
a fourth transistor with its base connected to receive said first clock signals;
a second plurality of other transistors, each of said second plurality of other transistors having its base con-nected to receive one of a second group of said plurality of input signals, the collectors of said second plurality of other transis-tors commonly connected to said first reference voltage means;
second resistive means commonly connecting the emitters of said third, fourth, and second plurality of other transistors to said third reference voltage means;
24.
a fifth transistor with its base connected to said second reference voltage means;
a sixth transistor with its base connected to receive said second clock signals;
a seventh transistor with its base connected to the collector of said fifth transistor, the collectors of said sixth and seventh transistors commonly connected to said first reference voltage means;
third resistive means commonly connecting the emitters of said fifth, sixth and seventh transistors to said third reference voltage means; and fourth resistive means coupling the collectors of said first, said third and said fifth transistors to said first reference voltage means.
Claim 8 - The circuit as claimed in Claim 7 wherein each of said storage means further comprises:
an eighth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said fourth resistive means to said third reference voltage means.
an eighth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said fourth resistive means to said third reference voltage means.
Claim 9 - A current mode logic register system comprising:
a clock circuit for generating complementary first and second clock signals having a pulse width of fixed duration;
first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage signal of a level between said first and said second voltage signals;
a first plurality of parallel storage means responsive to said first and said second clock signals and connected to receive a plurality of input signals, each of said first plurality of storage means performing a logical operation on said input signals and storing the result of said logical oper-ation, each of said first plurality of storage means comprising:
a first transistor with its base connected to said second reference voltage means;
a second transistor with its base connected to receive said first clock signals;
a first plurality of other transistors, each of said first plurality of other transistors having its base con-nected to receive one of a first group of said plurality of input signals, the collectors of said first plurality of other transis-tors commonly connected to said first reference voltage means;
a first resistive means commonly connecting the emitters of said first, second and first plurality of other transistors to said third reference voltage means;
a third transistor with its base connected to said second reference voltage means;
a fourth transistor with its base connected to receive said first clock signals;
a second plurality of other transistors, each of said second plurality of other transistors having its base con-nected to receive one of a second group of said plurality of input signals, the collectors of said second plurality of other transis-tors commonly connected to said first reference voltage means; and second resistive means commonly connecting the emitters of said third, fourth, and second plurality of other tran-sistors to said third reference voltage means;
a fifth transistor with its base connected to said second reference voltage means;
a sixth transistor with its base connected to 26.
receive said second clock signals;
a seventh transistor with its base connec-ted to the collector of said fifth transistor, the collectors of said sixth and seventh transistors commonly connected to said first reference voltage means;
third resistive means commonly connecting the emitters of said fifth, sixth and seventh transistors to said third reference voltage means; and fourth resistive means coupling the collectors of said first, said third and said fifth transistors to said first reference means; and a second plurality of parallel storage means responsive to said first and said second clock signals and con-nected to receive at least one input signal, each of said second plurality of storage means comprising;
an eighth transistor with its base coupled to said second reference voltage means;
a ninth transistor with its base connec-ted to receive said second clock signals;
a tenth transistor with its base connec-ted to the collector of said first transistor, the collectors of said ninth and said tenth transistors commonly connected to said first reference voltage means;
fifth resistive means commonly connecting the emitters of said eighth, ninth and tenth transistors to said third reference voltage means;
an eleventh transistor with its base connected to said second reference voltage means;
a twelfth transistor with its base con-nected to receive said first clock signals;
a thirteenth transistor with its base 27.
connected to the collector of said eleventh transistor, the collectors of said twelfth and thirteenth transistors commonly connected to said first reference voltage means;
sixth resistive means commonly connecting the emitters of said eleventh, twelfth and thirteenth transistors to said third reference voltage means; and seventh resistive means coupling the collectors of said eighth and said eleventh transistors to said first reference voltage means.
a clock circuit for generating complementary first and second clock signals having a pulse width of fixed duration;
first, second and third reference voltage means, each of said reference voltage means producing a corresponding first, second and third voltage signal, said second voltage signal of a level between said first and said second voltage signals;
a first plurality of parallel storage means responsive to said first and said second clock signals and connected to receive a plurality of input signals, each of said first plurality of storage means performing a logical operation on said input signals and storing the result of said logical oper-ation, each of said first plurality of storage means comprising:
a first transistor with its base connected to said second reference voltage means;
a second transistor with its base connected to receive said first clock signals;
a first plurality of other transistors, each of said first plurality of other transistors having its base con-nected to receive one of a first group of said plurality of input signals, the collectors of said first plurality of other transis-tors commonly connected to said first reference voltage means;
a first resistive means commonly connecting the emitters of said first, second and first plurality of other transistors to said third reference voltage means;
a third transistor with its base connected to said second reference voltage means;
a fourth transistor with its base connected to receive said first clock signals;
a second plurality of other transistors, each of said second plurality of other transistors having its base con-nected to receive one of a second group of said plurality of input signals, the collectors of said second plurality of other transis-tors commonly connected to said first reference voltage means; and second resistive means commonly connecting the emitters of said third, fourth, and second plurality of other tran-sistors to said third reference voltage means;
a fifth transistor with its base connected to said second reference voltage means;
a sixth transistor with its base connected to 26.
receive said second clock signals;
a seventh transistor with its base connec-ted to the collector of said fifth transistor, the collectors of said sixth and seventh transistors commonly connected to said first reference voltage means;
third resistive means commonly connecting the emitters of said fifth, sixth and seventh transistors to said third reference voltage means; and fourth resistive means coupling the collectors of said first, said third and said fifth transistors to said first reference means; and a second plurality of parallel storage means responsive to said first and said second clock signals and con-nected to receive at least one input signal, each of said second plurality of storage means comprising;
an eighth transistor with its base coupled to said second reference voltage means;
a ninth transistor with its base connec-ted to receive said second clock signals;
a tenth transistor with its base connec-ted to the collector of said first transistor, the collectors of said ninth and said tenth transistors commonly connected to said first reference voltage means;
fifth resistive means commonly connecting the emitters of said eighth, ninth and tenth transistors to said third reference voltage means;
an eleventh transistor with its base connected to said second reference voltage means;
a twelfth transistor with its base con-nected to receive said first clock signals;
a thirteenth transistor with its base 27.
connected to the collector of said eleventh transistor, the collectors of said twelfth and thirteenth transistors commonly connected to said first reference voltage means;
sixth resistive means commonly connecting the emitters of said eleventh, twelfth and thirteenth transistors to said third reference voltage means; and seventh resistive means coupling the collectors of said eighth and said eleventh transistors to said first reference voltage means.
Claim 10 - The circuit as claimed in Claim 9 wherein each of said first plurality of storage means further comprises:
a fourteenth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said fourth resistive means to said third reference voltage means;
and wherein each of said second plurality of storage means further comprises:
a fifteenth transistor with its base responsive to said reset signal, its collector connected to said fifteenth reference voltage means, and its emitter connected by said seventh resistive means to said third reference voltage means.
a fourteenth transistor with its base responsive to a reset signal, its collector connected to said first reference voltage means, and its emitter connected by said fourth resistive means to said third reference voltage means;
and wherein each of said second plurality of storage means further comprises:
a fifteenth transistor with its base responsive to said reset signal, its collector connected to said fifteenth reference voltage means, and its emitter connected by said seventh resistive means to said third reference voltage means.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/636,861 US3984702A (en) | 1975-12-02 | 1975-12-02 | N-bit register system using CML circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1066369A true CA1066369A (en) | 1979-11-13 |
Family
ID=24553646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA265,553A Expired CA1066369A (en) | 1975-12-02 | 1976-11-12 | N-bit register system using cml circuits |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3984702A (en) |
| JP (1) | JPS5268335A (en) |
| BE (1) | BE848990A (en) |
| CA (1) | CA1066369A (en) |
| DE (1) | DE2654190A1 (en) |
| FR (1) | FR2334242A1 (en) |
| GB (1) | GB1506338A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5913118B2 (en) * | 1978-12-11 | 1984-03-27 | ハネイウエル・インフオメ−シヨン・システムス・インコ−ポレ−テツド | J-K style master/slave register with additional reset and non-functional test capabilities |
| US4311925A (en) * | 1979-09-17 | 1982-01-19 | International Business Machines Corporation | Current switch emitter follower latch having output signals with reduced noise |
| US4495629A (en) * | 1983-01-25 | 1985-01-22 | Storage Technology Partners | CMOS scannable latch |
| FR2581811A1 (en) * | 1985-05-10 | 1986-11-14 | Radiotechnique Compelec | NUMERIC MULTIPLEXER MODULE WITH N INPUTS AND MULTIPLEXER WITH N2 INPUTS INCORPORATING SUCH MODULES |
| JPH0683054B2 (en) * | 1985-12-20 | 1994-10-19 | 日本電気株式会社 | Logic level conversion circuit |
| US5130578A (en) * | 1989-11-30 | 1992-07-14 | Hughes Aircraft Company | Efficient high speed N-word comparator |
| US5130568A (en) * | 1990-11-05 | 1992-07-14 | Vertex Semiconductor Corporation | Scannable latch system and method |
| US6188260B1 (en) | 1999-01-22 | 2001-02-13 | Agilent Technologies | Master-slave flip-flop and method |
| US7215170B1 (en) * | 2003-09-16 | 2007-05-08 | Cypress Semiconductor Corp. | Low voltage logic circuit with set and/or reset functionality |
| US9490783B1 (en) * | 2015-04-15 | 2016-11-08 | Texas Instruments Incorporated | Area efficient multi bit flip flop topologies |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3321639A (en) * | 1962-12-03 | 1967-05-23 | Gen Electric | Direct coupled, current mode logic |
| US3505535A (en) * | 1967-01-03 | 1970-04-07 | Ibm | Digital circuit with antisaturation collector load network |
| US3535546A (en) * | 1968-02-12 | 1970-10-20 | Control Data Corp | Current mode logic |
| US3539824A (en) * | 1968-09-03 | 1970-11-10 | Gen Electric | Current-mode data selector |
| US3599184A (en) * | 1969-07-10 | 1971-08-10 | Rca Corp | Storage circuit |
| DE1941264C3 (en) * | 1969-08-13 | 1975-07-17 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Asynchronous RS flip-flop in ECL technology |
| US3740590A (en) * | 1971-12-17 | 1973-06-19 | Ibm | Latch circuit |
| US3760190A (en) * | 1972-06-29 | 1973-09-18 | Ibm | Non-current summing multiple input latching circuit |
-
1975
- 1975-12-02 US US05/636,861 patent/US3984702A/en not_active Expired - Lifetime
-
1976
- 1976-11-12 CA CA265,553A patent/CA1066369A/en not_active Expired
- 1976-11-30 DE DE19762654190 patent/DE2654190A1/en not_active Withdrawn
- 1976-11-30 JP JP51143952A patent/JPS5268335A/en active Pending
- 1976-12-02 BE BE172906A patent/BE848990A/en not_active IP Right Cessation
- 1976-12-02 FR FR7636371A patent/FR2334242A1/en active Granted
- 1976-12-02 GB GB50251/76A patent/GB1506338A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5268335A (en) | 1977-06-07 |
| FR2334242B1 (en) | 1982-09-24 |
| GB1506338A (en) | 1978-04-05 |
| US3984702A (en) | 1976-10-05 |
| BE848990A (en) | 1977-04-01 |
| DE2654190A1 (en) | 1977-06-23 |
| FR2334242A1 (en) | 1977-07-01 |
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