SU419892A1 - - Google Patents

Description

The device relates to the field of digital computing and can be used in digital computers, in information retrieval systems, in systems for collecting and processing information.

In modern real-time computing systems, buffer fillers are used to match data flows between different devices, which are usually allocated to separate zones in the storage device (called buffer zones).

Devices of a similar type are known, which include counters for the formation of an address below and readout into a buffer zone, a comparison circuit, a channel switch, a control circuit. The presence of autonomous memory in the exchange device is not critical, since the memory of the exchange device can be organized in the memory of the system.

A disadvantage of the known device is the lack of control over the degree of filling of buffer zones during the exchange in both directions.

In order to expand the functionality, the device contains a state generation unit and a reversible counter, first its input is connected to the first output of the control unit, the second input is connected to the second output of the control unit, the third input

2

and the first output is connected to the device bus, the second output is connected to the first input of the state generation unit, the output of which is connected to the control unit.

This makes it possible to control the filling wall of the buffer zones of the exchange in both directions.

The drawing shows the structural scheme of the proposed device.

The exchange device contains a summing counter 1 and a reversible counter 2, a summing counter 3, a register 4, a signal generation unit of state 5, a channel selector b, a control unit 7, numerical and adjustment buses 8-16.

Binary counter 1 is assigned to form the absolute address of the write to the buffer zone, and counter 3 is used to form the absolute address of the read from the buffer zone. Reversible binary counter 2 is designed to count the number of units of information currently in the buffer zone. Register 4 is used to fix the volume of the buffer zoo. The state-of-the-art signal generation unit 5 is designed to generate signals that display the varying degrees of overlap buffer zones and a number of critical buffer states. The switch, channel 6, is designed to support the flow of applications from system devices to

according to their priorities and the formation of address addresses to the memory cells of the exchange device fixed for each device. The control unit 7 is designed to generate control signals in accordance with a predetermined algorithm of functioning of the exchange device.

Before the exchange between two devices of the system (one of them is the receiver, the other is the source of information), they are assigned a common buffer zone, which is assigned a certain number. The number of specified buffer zones that the exchange device controls is determined mainly by the memory of the exchange device. The exchange device memory is necessary for storing the current states of counters 1, 2, 3 and register 4 while simultaneously managing several buffer zones. (In the following, the contents of a memory cell storing the current state of counters 1, 2, 3 and register 4 will be called the control word.)

Before working in the field of the memory cell of the exchange device, the storage space for the contents of counters 1 and 3 is filled in with the base addresses defining the location of the buffer zones; in the field for storing the contents of counter 2 - "zeros", and in the field for storing the contents of register 4 - a binary code defining the volume of the buffer zone. The volume of a zone is determined by the number of units in the lower bits of the field allocated for storing the contents of register 4. If the number of units in the lower bits is n, then the volume of the buffer zone is 2 pieces of information. In the exchange device, the formation of the current absolute address of the write or read is accomplished by adding the code relative to the address to the code of the base address. The formation of relative addresses specifying the location of the current cell of the buffer zone is carried out in those bits of counters 1 and 3, which correspond to units in register 4. This part of counters 1 and 3 operates in a ring mode. “The units in register 5 allow the transfer from the same bits of counters 1 and 3 to the next highest ones. The bits of counters 1 and 3, which correspond to the zero field of register 4, do not change, as a result of which the base address remains constant throughout the entire exchange session.

The number of information units currently in the buffer zone is determined by the contents of the reversible counter 2. When writing information to the buffer zone, the contents of counter 2 increase by one, and when read from the buffer zone, decrease by one. Analysis of the degree of zapolpeni and generation of a number of state signals is carried out taking into account the volume of the buffer zone by node 5.

Requests from various devices for receiving or transmitting information are received by the servers 10. At the same time receiving several applications, the channel selector 6 selects the highest priority file, places on the buses AND the code of the device number 5 and prepares its input circuits for receiving the address with address buses 9. The device, whose number is set on tires 11, sends to the channel switch the number of the buffer zone and the operation code

0 (write or read). The switch of channels 6 according to the zone number forms a command for accessing the memory of the exchange device. This command reads the zone control word and writes its components to counters 1, 2, 3 and register 4. If the operation code is "write to" in the current service cycle, control unit 7 analyzes the state of the corresponding buffer zone (status information). nii zone enters

0 along the tongue 15). If the buffer zone is not completely filled, then the control unit allows recording, connects counter 1 to the address buses, and to numeric digits - the information output of such a device, the number of which

5 is set up on the buses 11. After completing these switchings, information is recorded in the memory at the address contained in counter 1, then one is added to counters 1 and 2. The modified values of counters 1, 2, as well as the values of counter 3 and register 4, are sent to a fixed cell reserved for the current control word. With the arrival of a signal on bus 13, indicating the end of the memory operation, the device exchanged on bus 14 issues a signal to the currently serviced device that the application is being executed. If during servicing of the application one of the specified states of the buffer zone occurred, then

0, the occurrence of the situation is reported to the serviced device by sending an appropriate signal through one of the strings of 15. At the same time, the application execution signal is issued. When trying to serve

5 devices write information to the fully filled buffer zone; state unit 5 generates a signal "full, which goes to one of the buses 15. With this signal, the control unit 7 prohibits writing to the buffer zone and generates a failure signal on the bus 16, signaling the device that it is impossible to perform his for vki.

If in this service cycle a read code is set, the control unit 7 analyzes the status signals on the ladies 15. If there is no signal on the buses 15, the buffer of the exchange device organizes reading from the buffer zone at the address stored in the counter 3. For this the control node connects the outputs of the counter 3 to the address buses, and the inputs of the device currently being serviced to the number buses, and organizes access to the memory. The device, the number of which is set in 5 11 11, accepts the requested information arriving on numeric buses. With the arrival of the signal on bus 13, one is added to the contents of counter 3, and one is subtracted from the contents of counter 2. The modified values of counters 2, 3, as well as the contents of counter 1 and register 4, are sent to a fixed memory location reserved for the current control word. Then, just as with the recording of information, the control node generates a signal at the bus 14 for the end of the service and gives permission for the transition to servicing the application from other devices.

Subject invention

An interchange device containing counters that form addresses that are connected to

address and numeric device strings and with the control unit connected to the channel switch, n volume buffer register, connected; the first with the numeric bus and counters formed addresses, characterized in that, in order to distribute the functional capabilities of the device, it contains a generation unit states and a reversible counter, the summing input of which is connected to the first output of the control unit, the subtraction input - with the second output of the unit is equalized, the bit inputs - with the numeric device bus, the second output - with the first input m of the state generation unit, the output of which is connected to the third input of the control unit and the output of the buffer volume register.