SU385394A1 - ANALOG-DIGITAL CONVERTER - Google Patents

Description

The invention relates to an analog-to-digital converter technology, namely, to an electrical signal converter in binary code. Such devices are used in various measuring channels of automation, input devices of specialized digital computers, analyzers, etc. The analog-to-digital converter is known, containing an input signal expander and comparison laughter, the outputs of which are connected to the same inputs, their anti-coincidence circuits and through time elements delays - to the second inputs of the corresponding anti-coincidence schemes of the lower bits, information retrieval valves, driver, adder, start and reset circuits, reference keys with zap Minani. In each channel of such converters, there is, along with the most senior, an analog adder of weight signals (code-analog converter), the number of inputs of which grows as it approaches the lower channel. This leads to a reduction in the conversion accuracy, since instabilities in the weighting signal circuits of each channel, especially older ones, appear in all channels. The lack of unification of the sources of weight signals according to the load capacity also limits the size of the output code. The proposed device differs from the known ones, in order to increase the conversion accuracy, in it the outputs of the anti-coincidence circuit are connected to the inputs of the adder connected between the output of the input expander and the inputs of the comparison circuits, and the inputs of the corresponding information retrieval gates Yush, whose inputs are connected to the output of the imager; the last input through time delay elements is connected to the last but one output, starting with the highest one, the comparison circuit and to the input of the reset circuit, one output of which is connected to control inputs of the reference keys with memory, the other with the comparison circuits and the third one with the input signal expander; the second input of the higher anti-coincidence circuit is connected via the trigger circuit to the output of the input expander. FIG. 1 shows a four-bit functional diagram of the converter; in fig. Figure 2 shows the arrangement of reference voltage levels of the comparison circuits, where, according to the invention, level / 2 corresponds to the upper channel, D to the younger channel, etc., and two examples of conversion processes described below (curves a b) are illustrated. At the input of the converter (Fig. 1) stands

an expander of the input pulses /, which stores the amplitude of the pulse or the instantaneous value of the voltage at the conversion time. From here, the signal goes through analog adder 2 at the same time to the inputs of all comparison circuits 3-6 that are tuned to levels

/ 2, 3/4,

alarms distributed as - / 2,

/ 8 AND 1S / 16 FROM the maximum of the input signal as it approaches the lower channel (Fig. 2). The outputs of adjacent comparison circuits are commuted to anti-supervised 7-10 circuits, which only work if only the comparison circuit of the previous channel has switched. To the outputs of the anti-coincidence circuits, the // // 14 reference keys are connected, remembering their state when switching. If the corresponding anti-coincidence scheme is triggered, the keys issue a feedback signal to the common adder 2; the channel weights are distributed similarly to the comparison and subtraction method, i.e., as / 2, / 4, Vs from the maximum of the input signal as it approaches the lower channel} . The anti-matching schemes 8-10 are connected with the comparison schemes of the previous channel 5-5 through the elements of the time delay 15-17, which prevents the false operation of one of the anti-matching schemes in case of switching on any conversion circuit of the two comparison circuits connected to it.

If the input signal does not exceed the reference level of the older channel, the converter is triggered by the start-up circuit 18. The information is removed from the information outputs of the reference keys through the removal valves 19–22 using the signal from the penultimate comparison circuit 5, which is delayed by delay elements 17 and 23 and formed on the driver 24. The circuit returns to the initial state by the reset circuit 25 by the same signal, additionally delayed by the delay element 26.

Depending on the amplitude of the input pulse received at the inputs of all comparison circuits 3-6, at the first conversion step, any number of them can be switched from O to 4., .o., And f one comparison circuit does not work (Fig. 2, curve a). After a time, determined by the length of the front of the input signal and the delay in the comparison circuit 3, a trigger is sent from the starting circuit 18, from which the anti-match 7 operates. The reference key 11, switching, fixes its new state and gives the output 2 equal to the weight of the older channel, i.e. / 2 in, „a1- A code is set at the information key output

Depending on the amplitude of the input signal from the sum of bvx + L in, obtained at the output of adder 2, "at the second conversion step any number of comparison circuits, including the comparison circuit

5 (when an increment is fed to the input of the adder, at least the comparison circuit of the channel that gave this increment is triggered). When switching higher comparison circuits 5 and

the anti-matching circuit 8 cannot be triggered, since the inhibit signal from the comparison circuit 4 arrives. even earlier than the delayed signal from the comparison circuit 3 delayed on the delay element 15.

There are no changes in the anti-matching scheme 10, since according to the assumption the comparison schemes 5 and 5 do not switch on this conversion node. In the anti-match 9 scheme, the delayed

on the delay element 16, the resolving signal from the comparison circuit 4, and it is triggered, including the reference key 13. Thus, a string is selected from the failed comparison circuits 5. On the information output

The key 13 is set to the code "O, and at the output of SumAlator 2 a new increment appears, equal to the weight of the third channel, i.e. Vs, ah

From the amount received / their + / 2 .pah

, Comparison circuit 5 is triggered by all means, the state of comparison circuit 6 is determined by the value of f / ix (Fig. 2, full or dashed curve a.). If it switches, the anticoincidence circuit 10 is locked, otherwise it is unlocked by resolution, 5, set at the output of the key 14 code "O.

If the input signal f / ix exceeds / 2 (Fig. 2, curve b), the anti-coincidence circuit 7 is locked until the start pulse arrives from the trigger circuit 18, and the highest of the non-operating reference circuits is sampled automatically cpa3j after the leading edge of the input signal

and the operation of all previous comparison schemes. Further, the processes proceed in the same order.

Thus, if any reference key 11-14 is triggered, the anti-matching circuit code is set on its information output and could not be started (for example, anpis coincidence circuit 8 in the first example), the " 1. The output code at the information outputs of the keys is set the faster, the less often you have to submit increments to the inputs of adder 2, i.e., the fewer characters "O in the code of the signal being converted. In addition, upon completion of the conversion, all n-1 higher comparison circuits (i.e., 3-5) are switched (Fig. 2, curves a and b). This makes it possible to record the moment when the conversion ends and to carry out an asynchronous mode of operation of the converter with information retrieval by a signal from the penultimate comparison circuit 5, delayed by delay elements 17- and 23 to detect the final state of the comparison circuit 6 and the key 14. This signal is formed shaper 24 and opens