SU382127A1 - ALL-UNION FLATEHTHO-TEXliri ^ C ^ B? - Google Patents

Description

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The invention relates to the field of telemechanics and is intended for receiving telecontrol signals transmitted from the head locomotive on a locomotive located in the middle of the train.

Remote control receivers are known that contain a frequency receiver, the outputs of which are connected to the inputs of the decoder made on coincidence circuits, intermediate memory triggers, one of the inputs of which is connected through the first inverter to the first output of the decoder, and the other to the second and third outputs of the decoder, respectively actuating relays with normally open contacts, the windings of which are connected to the outputs of the coincidence circuits, the first inputs of which are connected to one of the outputs of the trigger PA ti, the reset relay winding is connected to the fourth output of the decoder through a second inverter.

A disadvantage of the known devices is the low reliability of operation.

To eliminate this drawback, a signal reception trigger, an OR circuit, an additional inverter and diodes are introduced into the device, one of the inputs of the signal reception enable trigger is connected to the output of the first inverter, and the other to the output of the second inverter and

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to the second inputs of the matching circuits, and the output of the signal enable trigger is connected to the third inputs of the matching circuits and through the first diode to the fourth output of the decoder; the outputs of the flip-flops of the intermediate memory are connected to the inputs of the “ILR1” circuit, the output of which is connected via a series-connected dovolt inverter and the second diode is connected to the fourth input of the decoder.

The schematic diagram shows the schematic of the proposed device.

Etc; A remote control device includes a frequency receiver /, to the outputs 2, 3, 4, 5 of which a binary code decoder is connected for one combination, made on a diode circuit 6, 7, 8, 9 matches. The output of the coincidence circuit 6 is connected via an inverter 10 to the input of the trigger 11 for receiving signals, the output of which is connected to the inputs of the circuits 12 and 13 coinciding and through the diode 14 to the circuit 9 and from the inputs of the triggers 15 and 16 of the intermediate memory. Circuit outputs

7, 8 matches are connected to other inputs of the flip-flops 15, 16 of the intermediate memory, the outputs of which are connected to the inputs of the circuits 12, 13 of the match, as well as through the OR 17 logic circuit, the additional inverter 18 and the diode 19 to the coincidence circuit 9.

The output of the coincidence circuit 9 is connected via an inverter 20 to a coil of a reset relay 21 having one normally open contact 22, with inputs of the co-ownership circuits J2, 13 and to the trigger input 11. The outputs of the coincidence circuit 12, 13 are connected to the coils of the executive relays 23, 24, having respectively normally open contacts 25 and 26 self-blocking. Diodes 27, 28, 29, connected in parallel to the coils of the corresponding relays 21, 23, 24, serve to eliminate the extracts that occur when the coils are disconnected. Resistance 30 limits the current through the coils of the relay 23, 24.

The remote control receiver operates as follows.

In the initial state of the circuit 6, 7, 8, 9, the coincidence is locked, the relay 21 is energized and its contact 22 is closed. The command coming from the control room and arriving at the input of the frequency receiver contains three pulses; coming successively in time.

The first impulse arrives on the ladders 2, 3 of the decoder (negative potential), the coincidence circuit 6 opens and the negative potential from its output through the inverter 10 transfers the trigger 11, which enables the operation of the circuits 12, 13 coincidences and through the diode 14 - the operation of the circuit 9. The 15 / b memory returns to its original state.

The second impulse arrives at the busbars 2, 5 of the decoder (or the busbars 2, 4), allowing the operation of the circuit 13 to coincide and through the logic circuit OR 17, the inverter 18 and the diode 19 - the operation of circuit 9.

The third pulse arrives at the busbars 3, 4 of the decoder, the diode circuit 9 opens. The negative potential from the output of the circuit 9 goes through the inverter 20 to the coil of the relay 21, the contact 22 opens, dropping the relay 23, if it was, previously excited. At the same time, the diode circuit 13 opens and the coil of the relay 24 is energized by the circuit: plus a power source - the coil 24 - the circuit 13. If the coil of the relay 24 has been energized before, it does not lose power and the contact 26 will remain closed.

After the end of the pulse, the coil of the relay 21 is energized, the contact 22 closes, the coincidence circuit 12 closes and the coil 24 is still energized along the circuit: plus power supply — coil 24 — contact 26 — resistance 30 — contact 22 minus the power supply. At the same time, trigger 11 returns to the initial state.

If at least one of the pulses coming from the line is missing, the circuit will remain in the same state until the next command arrives.

Subject invention

A remote control receiver containing a frequency receiver, the outputs of which are connected to the inputs of the descrambler,

made in the coincidence circuits, triggers of the intermediate memory, one of the inputs of which is connected through the first inverter to the first output of the descrambler, and the other to the second and third outputs of the decoder

accordingly, executive relays with normally open contacts, the windings of which are connected to the outputs of the coincidence circuits, the first inputs of which are connected to one of the outputs of the intermediate memory trigger, a reset relay, the winding of which is connected to the fourth output of the decoder via a second inverter, characterized in that , in order to improve the reliability of the device, it introduced a signal enable trigger, an OR circuit, an additional inverter and diodes, one of the inputs of the signal enable trigger being connected The output to the output of the first inverter and the other to the output of the second inverter and to the second inputs of the matching circuits, and the output of the signal enable trigger are connected to the third inputs of the matching circuits and through the first diode to the fourth output of the decoder; the outputs of the intermediate memory flip-flops are connected to the inputs of the OR circuit, the output of which is connected through a series-connected additional inverter and the second diode is connected to the fourth input of the decoder.