SU362264A1 - UNIVERSAL1? :; mmm-'iim ^ z w :: -: - Google Patents

Description

one

The invention relates to the field of radar.

The known pulse sequence detector contains a binary quantizer, one output of which is connected to the summing input of a reversible counter, while the output of the reversing counter is connected to the series-connected upper threshold circuit and zeroing circuit connected to the zero-setting counter input.

The aim of the invention is to increase the likelihood of detecting a sequence of pulsed signals with continuous movement of the antenna beam.

This is achieved by additionally introducing a zero registration circuit, the input of which is connected to the output of a reversible counter, and a "inhibit" circuit, one input of the "inhibit circuit" connected to the output of the zero registration circuit, the other to the output of the "NOT whose input is connected to another output of the binary quantizer, and the output of the prohibition circuit is connected to the subtractive input of the reversible counter. .

The drawing shows a block diagram of the proposed device.

The proposed device includes a quantizer /, a reversible counter 2, a logic circuit 3 "NOT, a prohibition scheme 4", a circuit 5 of the upper numerical threshold, a circuit 6 for zeroing the reversible counter, a circuit 7 for registering zero in the counter. The device works as follows.

In the event that the quantizer quantizing threshold / voltage is exceeded from the receiver output at the moment the counting pulse arrives, the summing input of the reversible counter 2 receives a signal and the number written

in the counter, the number r is added. If, in a given recurrent period, the quantization threshold in the considered discrete is absent, then at the moment of arrival of the counting pulse through the scheme 3 "NOT and the prohibition scheme 4"

the subtracting input of the reversible counter 2 receives a signal, and one is subtracted from the number in the reversible counter. When the counter (2) reaches the upper (positive) numerical threshold, circuit 5 outputs a signal

The detection and signaling zeroing circuit 6 returns the counter to its original zero state. If the number in the counter is zero, then the circuit 7 for registering the zero state of the counter produces a zero signal

state on the scheme 4 "prohibition and prohibits the subtraction of units from the number recorded in the counter (zero is recorded in the counter). In the absence of signals from the target, the number in the reversible counter will not significantly differ from zero, since the quantization threshold is exceeded by the voltage voltage with a low probability determined by the height of the threshold. When a pulse burst of signals from the target appears, the probability of exceeding the quantization threshold increases, and the number in the counter begins to increase. If the signal power (i.e., the probability of exceeding the quantization threshold) and the burst duration are sufficient for the number in the counter to reach the upper threshold during the burst time, then such a signal will be detected.

Subject invention

A pulse sequence detector that contains a binary quantizer, one output of which is connected to the summing input of a reversible counter.

the output of the reversible counter is connected to a series-connected upper threshold circuit and a zero circuit connected to the zero-reset input of the reversible counter, characterized in that, in order to increase the likelihood of detecting a sequence of pulsed signals when the antenna beam moves continuously, a recording circuit is introduced zero

the input of which is connected to the output of the relay counter, and the inhibit circuit, one input of the inhibit circuit connected to the output of the zero registration circuit, the other to the output of the NOT circuit, whose input is connected to another output of the said binary quantizer, and the output of the inhibit circuit connected to the subtracting input of the reversible counter.