SU268753A1 - DEVICE FOR PROCESSING INFORMATION - Google Patents

Description

i:

The invention relates to the field of preprocessing devices for information obtained during the registration of various processes, and can be applied in designing information storage and processing devices.

Information processing devices are known that contain a storage unit with an address register, address keys and memory elements, an arithmetic unit including a register of a digit with a sign bit, and an adder with a first and a second sign bit and also contains a control unit.

The proposed device contains an impulse-potential key, one of the potential control inputs of which is connected to the output of the second sign bit of the adder, two other control potential inputs via a trigger, and a control pulse input directly connected to the control unit, two pulse outputs of the key are connected with the counting inputs of the register of the number and the adder, the command output of the control unit is connected to the zero-channel address selection width and the address keys are disabled via the trigger and the selection key channel address zero, the resetting to zero of tires of the register and sign bit of that register and the reset of tires

to the zero of the adder with the first sign bit and the second sign bit of the adder are separately connected to the command outputs of the control unit.

The drawing shows a block diagram of the device information processing.

The device contains a storage unit 1, an arithmetic unit 2, a control unit 3, a pulse-potential key 4, a trigger 5

controlling the pulse-potential key, trigger 6 controlling the key for selecting the address of the zero channel and key 7 for selecting the address of the zero channel.

Memory block 1 consists of a register

8 addresses, address keys 9 and memory elements 10, and arithmetic unit 2 — from register // number, adder 12, sign bit 13, register of number and sign bits 14 and 15 of the adder.

The address register 8 is connected with the potential inputs of flip-flops to the inputs of the address keys 9, the outputs of which are connected to the memory elements 10. The pulse outputs of the storage unit are connected to the pulse ones

the trigger inputs of the register are 11 numbers, the pulse outputs and the inputs of which are associated with the pulse inputs and outputs of the adder 12, respectively. The output of the last high-priority trigger of the number register is connected to the input inputs of this bit position and the number register is separately connected to control unit 3. The output of the last accumulator trigger is connected to the countable input of the sign bit 14, the output of which is connected to the counted input of the sign bit 15, moreover, the input of setting the zero of the sign bit 15 separately from the input of the installation of the zero of the adder and the sign bit 14 is connected to the control unit. The pulse output of the sign bit 13 is connected to the pulse inputs of the sign bits 14 and 15. The potential output of the sign bit 15 is connected to the pulse-potential key 4, the first output of which is connected to the counting input of the adder, and the second one - to the counting input of the number register. Key control trigger 5 5 connects two potential outputs to the potential inputs of this key, and pulse input key 4 connects to a control unit. The pulse inputs of the trigger 5 are connected to the control unit. With unrav-block. The pulse inputs of the trigger 6 for accessing the zero channel are also connected, the first potential output of which is connected to the input of the key 7 for selecting the address of the zero channel, and the second output to the address keys 9.

The processing device operates as follows.

As an example, it is assumed that the capacity of one channel of the storage unit 218 is I. All operations that are discussed below are performed according to a program using software pulses generated by the control unit.

When multiplying two numbers, the multiplicand is written in cell A of memory elements 10, the multiplier is in cell B, the result will be obtained in zero channel 0. Before performing the multiplication operation, the register / number is signed with a significant digit 13 and adder 12 with significant digits 14 and 15.

The key 4 is permanently connected by its pulse output to the counting input of the 11th register. The multiplication operation is as follows:

- refer to cell B of memory elements 10;

- reading from a cell In a multiplier (since the sign bit 13 is not connected with the storage unit /, then there will always be zero after the reading);

- shift by one bit of the multiplier in the register on the 11th, while the highest bit of the multiplier is in the sign bit 13:

- write to the cell In the remaining bits of the multiplier, while the 17-bit multiplier is in place of the 18-bit;

-set to zero register 11 numbers; no sign bit 13 is set to zero (the sign input of the sign 18 bit is blocked);

- refer to cell A of memory elements 10;

- reading from the cell A multiplicand;

-onros sign bit 13, if it contains one, then the transfer of multiplicand

in the adder parallel code; no significant bit 13 in the transmission is not involved;

-record the multiplier in the cell A;

-installation in the bullets register 11 numbers; - access to the zero channel;

- reading the number from cell 0;

- interrogation of the sign bit 15 via key 4, if the sign bit position 15 contains a unit, but as a result of summation, it doesn’t find the 11th number in the register input, i.e., add to the result;

-shift by one bit of contents: its register // number and adder 12;

- interrogation of the sign bit 15 via key 4, if there is a unit in it, then at the counting input it will turn into the result;

-record the result in the cell 0;

-set to the zero register of the 11th number and the sign bit 15.

The loop is then repeated 17 times and the product is obtained in the zero channel (at cell 0). When dividing two numbers, the dividend is written in cell A of memory elements 10, the divisor is in cell B, the result will be in zero channel 0. Before the division operation is performed, the register is preset to the 11th register number 11, adder 12 and sign bits 13- 15. Key 4 is controlled by trigger 5 during a division operation.

The division is made in the following order.

Preparatory operations:

- refer to cell A of memory elements 10;

- reading the dividend from cell A;

- transfer of the dividend from the register // number to the adder 12 and the sign bit 13 to the sign bits 14 and 15;

- write the dividend back to the cell A;

-set to zero register // number; Main loop:

- appeal to the cell B;

- reading divider from cell B;

-transfer divider from the register number // in the adder 12 in the opposite code, together with the sign 13; at the same time, the pulse output of the switch 4 is connected to the counting input of the adder 12; when the pulse output of the key 4 is connected to the counting input of the adder, overflow of the sign bit 15 passes to the counting input of the adder directly, without interrogating this bit;

- record divider cell B;

-set to zero register 11 numbers;

-application to the zero channel;