SU253451A1 - POSSIBLE-PERFORMANCE DEVICE - Google Patents

Description

The invention relates to computing.

The known methods and devices for the complex implementation of mathematical operations, involving the replacement of operations on numbers with operations on logarithms, require the use of special logarithmic converters that complicate the device and give only approximate logarithmic dependencies; in addition, after performing operations on logarithms, the results are subject to anti-logging.

The described invention allows mathematical operations on the natural logarithms of numbers without the use of logarithmic amplifiers.

This is achieved by applying discharge capacitor circuits with an initial charge and dynamically comparing the input values with the instantaneous value of the voltage on the capacitors.

The block diagram of the device is shown in the drawing, where: / and 3 are null organs; 2 and 4 — bit input circuits; 5 - bit of the resultant circuit; 6 - reversible counter; 7 — control unit; 8 - trigger pulse generator.

The input voltage Uj is applied to the nullorgan 1; its other input is supplied with the voltage from the output of the capacitor of the discharge circuit 2. The capacitor is precharged BEFORE the voltage UQ, if a multiplication operation is performed, or UQ to perform the operation

division.

With the help of the counter 6, launched from the generator of the starting pulses, it is remembered

time from the beginning of the discharge to the moment of the dynamic coincidence of the values of the input voltage and the voltage on the capacitor. After this operation is performed, the discharge of another bit circuit 4, the initial

voltage of which is Ug. The time that has passed from the beginning of the discharge to the instant that the second input voltage is equal to the voltage on the capacitor of the discharge circuit 4 is memorized by means of a counter 6.

If a multiply operation is performed, then the counter continues to count, adding to the accumulated information a new time value (i.e., the number of trigger pulses obtained during the first operation increases), and in the case of division, the counting pulses from

second comparisons are fed to reversing

the spars on the capacitor of the discharge circuit 4 determined by the null organ 3. After performing this operation, the trigger pulses are switched by block 7 to the reversing input, respectively, at multiply or remain on the reversing input upon dividing, and the discharge of the resulting circuit starts 5 (with the initial voltage of the resulting circuit being U respectively (f when multiplied and t / o when dividing) until all information from counter 6 is selected, i.e. the counter returns to zero. At this moment the discharge the resultant capacitor is terminated, and the voltage applied to it is output.

The voltage indicated is equal to the result of the mathematical operation being performed.

The sequence of all operations is controlled by block 7.

Subject invention

A multiplying-dividing device containing two null-organs, two-bit circuits, a reversible counter, and a control unit, characterized in that, in order to simplify and increase the accuracy of operation, one of the inputs of each null-organ is connected to the input source, the other input - to the output of the corresponding discharge circuit, and the output is connected to the input of a reversible counter connected to the input of the third discharge circuit, the output voltage of which is the desired result of multiplication (or division).