SU212362A1 - MEASURATOR OF AMPLITUDE-FREQUENCY AND PHASE-FREQUENCY CHARACTERISTICS OF FOUR-POLES - Google Patents

Description

Instruments are known that use tracking systems to automatically measure frequency characteristics. To ensure harmonic suppression, passive filters are used in devices after detection. Therefore, such devices have a large inertia.

Instruments are also known in which integration over a signal period is used to suppress the harmonics of a signal from a quadrupole. However, such devices have a small dynamic range for changes in the input signal level and, as a rule, operate in non-automatic mode.

The instrument uses a tracking system. But a discrete attenuator with electronic control was used as an actuator in the amplitude measurement channel, and the integrator for the period, working according to a special program, was included in the feedback circuit instead of a linear filter.

In the proposed meter, the integrator output is connected to a discrete attenuator through a series-connected memory device with a predictive discharge circuit and a locked pulse generator. A power supply is connected to the oscillating frequency oscillator tuning motor via a relay controlling winding

which is connected to a pulse generator.

For the integration time, while the error signal is generated, the feedback must be open. During the testing of the error by the attenuator, the feedback circuit is also open and there is no information about the completion of the processing required to stop the switching of the attenuator. The discharge circuit provides for the pulse generator to open for a time proportional to the error signal. The pulse repetition rate is chosen so that the number of switchings of the attenuator controlled by these

impulses, corresponding to the change in attenuation, compensating for the error signal.

FIG. 1 shows the block diagram of the described meter; in fig. 2 - a circuit diagram of a discrete digital attenuator with a code converter - analog; in fig. 3 - schematic diagram of the integrator for the period, the discharge device and the locked pulse generator; in fig. 4 is a diagram of the stopping of the engine frequency tuning generator.

The device contains (see Fig. 1) an infra-low frequency oscillator 1 of oscillating frequency, an amplitude measurement channel and a phase measurement channel. To the amplitude measurement channel, synchronous detector 3, integrator 4 for the period, back to the Power supply device 5 with a predictive discharge circuit, a locked pulse generator 6, an electronic pulse number counter 7, and a recording device 8. Phase measurement channel includes an electronically controlled phase shifter 9, a phase detector 10 and an integrator 11, a prediction device 12, a locked generator 13, similar to the ammeter measurement channel. The operation of the device as a whole is as follows. The signal from generator 1 is fed to the quadrupole 14 under study and simultaneously to the input of the phase shifter 9. After the quadrupole signal, the passage through the controlled attenuator 2 splits and goes to the detector 3 of the amplitude channel and the phase detector 10. The signal from the output of the phase shifter 9 is fed to the synchronous detector 3 and with a phase shift of 90 ° to the phase detector 10. At the output of the phase detector, a voltage is generated proportional to the phase shift introduced by the quadrupole 1 under investigation, which is an error signal for the next phase channel system. The following system treats this signal to zero by changing the phase shift introduced by the phase shifter, as a result of which the phase shifter of the phase shifter becomes equal to the phase shift introduced by the studied quadrupole. Therefore, the signals arriving at the detector 3 are in phase, which ensures its operation in the amplitude detection mode. The following system of the amplitude channel leads the signal at the output of the synchronous detector 3, and consequently, at the output of the attenuator 2 to a constant level, so that the change in attenuation of the attenuator corresponds to the change in the signal level from the output of the quadrupole. Attenuator 2 is made in the form of a chain of series-connected voltage dividers separated by key devices that turn on or off the corresponding voltage dividers depending on the presence of a control signal from the electronic control switch 7. Switch 7 is a binary counter, the voltage each bit of which controls the corresponding attenuator key. Each dividing cell of an attenuator has a transfer coefficient equal to), where 1 is the transfer ratio of the youngest bit and t is an integer equal to the weight of the corresponding binary bit in the counter. Thus, the attenuation coefficient of the attenuator can vary as K, where n is the number embedded in the counter. rehpoljusnika. The code converter, an analogue connected to counter 7, makes it possible to record the amplitude-frequency characteristic of a quadrupole in a logarithmic scale. The cycle of operation of integrators 4 and //, devices 5 and 12, and locked generators 6 n 13 is set by pulses that are formed from oscillations of generator 1 by amplifier-limiter 15. To reduce the dynamic errors of the device, the frequency tuning of generator 1 is stopped for a while a mismatch error is tested by the next systems of the amplitude and phase channels. For this, signals from the outputs of the locked pulse generators, the occurrence of which indicates the presence of a mismatch error, are fed through the device ILR 16 to the relay 17, which turns off the generator frequency tuning. Thus, each intermediate generator tuning cycle lasts until such time as the magnitude of the change in the transfer coefficient of the quadrupole exceeds the sensitivity threshold of the following systems. After the equilibrium of the servo system is restored, the adjustment process is resumed. Thus, the recorded frequency characteristics are stepwise, and the height of the steps is determined by the junior bit of the attenuator 2, and the frequency intervals between the steps are determined by the steepness of the frequency response of the quadrupole under study. The signal from the measured four-port 14 (see Fig. 2) is fed to the first cell of the attenuator consisting of resistances 18 and 19. From the cell of the attenuator, the signal can go in two ways: either through key 20 or through key 21. From keys 20 and 21, the signal arrives at the emitter follower 22, set to eliminate the effect of subsequent attenuator cells on the gain of the previous cells. From the output of the emitter follower 22, the signal goes to the next attenuator cell, which has a transmission ratio of 1 or 2, respectively. Keys 20 and 21 control trigger 23, keys 24 and 25 control trigger 26, etc. Triggers 23, 26, etc. . are connected to a reversible pulse counter, to the input of which a burst of impulses comes from a locked generator. The counter is reversed by switching the matching circuits 27 and 28. Transducer cells — an analogue consisting of resistances 29, 30, 31, and so on — are connected to one of the trigger outputs. From the converter output, the analog signal goes to the dial gauge, or to the input U of the two-coordinate recorder, and from the attenuator output - on amplitude

When a pulse pack arrives at the input of the counter, the counter after the end of their counting stops at the position corresponding to the number of pulses in the packet. Trigger-controlled keys set the attenuation in the attenuator cells according to the state of the meter triggers. The voltage from the output of the code-analog converter will correspond to the state of the meter triggers. Therefore, a definite voltage at the output of the converter corresponds to a certain attenuation of a discrete attenuator. If the attenuation in the cells is made in decibels, then from the output of the converter we obtain a voltage proportional to the attenuation of the attenuator in decibels.

The input of the integrator 4 (see Fig. 3), which is an operational amplifier with capacitive feedback, receives a signal from an amplitude (synchronous) detector. In order to ensure integration, a key 32 is turned on in parallel with the capacity of the integrator, which is controlled by a signal from the trigger 33 of the driver. From the integrator, the signal goes to a bit device, consisting of pass switches 34 and 55, bit capacitors and bit switches 36 and 37. From the bit output, the signal goes to the input of a locked generator, which consists of a direct count comparator 38, comparator 39 of the reverse counting, triggers 40, generating direct count pulses, and triggers 41, 42, 43 generating reverse count pulses, matching the emitter followers.

The trigger 33 generates a pulse, the duration of which is equal to the signal period. The impulse from the trigger closes the key 32 of the integrator and opens the pass keys 34 and 35. When the key 32 is closed, the signal is integrated. The signal from the integrator output through the open keys 34, 35 charges the capacitors 44 and 45. At the same time, the bit switches 36 and 57 and the comparators 38 and 39 of the forward and reverse count are locked.

During the next period, key 52 opens and discharges the capacitor of the integrator. At the same time, the pass switches 34 and 35 are closed and the discharge keys 36, 37 and the comparators 55 and 39 open. The capacitors 44 and 45 begin to discharge, respectively, through the keys 36 and 57. At the same time, if the signal was positive at the end of the integration, the comparator 55 is direct

the counting opens and begins to generate a burst of pulses, which, through combining circuit 46, enters the counting input of the pulse counter. At the same time, the same pulses are fed to the single input of the trigger 40. The pulse from the trigger is fed through the emitter follower to the coincidence circuit of the direct counting of the counter. The comparator remains open until

until the capacitor 44 is discharged to the threshold of locking the comparator 58. At the same time, the comparator 55 is locked because it opens with a negative voltage from the integrator output. Since the time of discharge of the copdator depends on the amplitude of the signal from the integrator, the number of pulses in the packet is proportional to the amplitude of the signal from the integrator.

The engine stop signal (a burst of pulses from a locked generator) is fed to a single engine trigger start input 47 (see FIG. 4), the signal from the trigger output switches the key 48, the load of which is the winding of the relay 49.

the relays commute the motor control winding circuit 50. In the next period of the signal, a clock start pulse of the engine arrives at the zero input of the trigger 47, which flips the trigger to the zero field: e. If a

the following stop pulses do not arrive after it, the engine starts frequency tuning.

Subject invention

35

The amplitude-frequency and phase-frequency characteristics of the quadrupoles in the infra-low frequency range, comprising a sweep frequency generator, a discrete attenuator and an integrator in the following system for testing the changes in amplitude and phase of the signal at the output of the quadrupole, characterized in that

speed and dynamic measurement range, the integrator output is connected to a discrete attenuator through a serially connected storage device with a predictive discharge circuit, a pulse generator and an electronic digital switch, and the power source is connected to the tuning frequency generator of the oscillating frequency generator through a relay whose control winding is connected to a pulse

to the generator.

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