SU205378A1 - - Google Patents

Description

METHOD OF ANALOG-DIGITAL TRANSFORMATION

Methods of analog-to-digital conversion are known, in which samples of a signal to be converted are sequentially compared with sawtooth voltages (currents) of the same duration (for example, smooth, stepped, etc.) and different slopes, as well as the ways in which each subsequent signal sample convert to completion of the previous one.

The proposed method is characterized in that, when forming intermediate digits of a code, the pedestal voltage obtained by the digital-analog conversion of the higher bits of the code is summed with the ramp voltage (current) of the slope corresponding to its definable discharge. This allows an increase in the quantization rate.

A / D conversion is performed as follows.

The next sampling of the signal is compared with the sawtooth voltage (current) of maximum steepness overlapping the entire conversion range, as a result of which the code digits of the higher bits are determined.

Then, by the high-order code using an additional set of standards, the weight of each of which is equal to the low-order weight of the high-order code, a pedestal voltage (current) that is different from the signal sample is not greater than

weights of this code. Pa this pedestal voltage (current) superimposes a sawtooth voltage of lesser slope and the same duration as the previous one, and overlapping part of the transformed range, equal to the weight of the least significant bit in the code of the most significant bits. As a result of the comparison, the code is determined in the bits following the elders, and so on, until

A sawtooth voltage (current) with a minimum slope is used, from which the digits of the low-order code are determined. At the same time, after determination by means of a sawtooth voltage (current), the maximum

the steepness of the digits of the code of the most significant bits of a given sample of the signal begins to determine the digits of the code of the higher bits of the next sample of the signal, etc. Moreover, if / ramp-like stresses are used, the speed

quantization increases v / times.

A block diagram of the converter that implements the proposed: 11 th method, for any number of bits with any combination and number of saw-tooth voltages (currents) of different inclinations

It is impossible to give in general form, therefore the drawing shows one particular example with n - 4 and two smooth sawtooth voltages.

two older bits (fourth and second) and, on the other, two lower bits (second and first). For l 4 and two sawtooth stresses (currents) two more inclinations are possible. In the first variant, codes in the fourth, third and second bits are determined from one sawtooth voltage (current), and from the first bit on the other. In the second variant, codes in the fourth bit are determined by one voltage and by the second in the third, second, and first bits.

An analog-to-digital converter consists of a cascade of higher and lower order bits.

The high-order cascade contains a generator of 1 sawtooth voltage (current) overlapping the entire conversion range, comparator 2, counter 3, account control trigger 4, valve 5, code removal AND 6-7 circuits, intermediate code storage triggers 8 , triggers W and // storing the code of the higher bits, keys 12-14 of the selection of signal samples, section 15-17 of the delay line.

The low order cascade contains a decoder 18, a set of standards 19–21 each weighing, keys, key control triggers 25–27, 28 saw voltage generator 28 spanning 1/4 of the input range, summing circuit 29, comparator 30, counter 31, trigger 32 of the control of the account, the valve 33, the circuit "And 34, 35 code retrieval, keys 36-38 selection signal samples, sections 39-41 delay lines.

A common part of all cascades is a generator of 42 pulses and a divider 43 of the pulse frequency of the generator in the ratio of 4: 1, having four outputs I, II, III, IV, with a phase shift of 0, 1, 2 and 3, respectively, of the pulse generator relative to output I.

Each section of the delay line delays by one pulse generator period 42.

The conversion is carried out as follows. In the cycle ti of the divider 43, a pulse from the output I triggers the generator /, translates to the state "1 flip-flop 4, and opens the key 12. At the same time, the comparator 2 is sampled Xf and sawtooth voltage (current). A sample of x is simultaneously fed to section 15 of the delay line. In addition, after the transition of the trigger 4 to the state "1", the valve 5 is opened through which the pulses of the generator 42 can pass to the counter 3.

Then, on one of the cycles fi, tn, / ni, keys 12-14 are opened, and the sawtooth voltage (current) reaches the sampling level l ;, the comparator 2 is activated, which returns the trigger 4 to the “O” state, which causes

to the closing of the valve 5. At the same time, the code 3 is fixed on the counter 3 in the fourth and third bits.

In step tiv, counter 3 and generator 1 are reset, and 6 to 7 circuits are opened, passing the code of the higher bits to the decoder 18. The code of the higher bits is also stored by triggers 8 and 9. The decoder 18, depending on the values of the digits of the code, converts to the state "One or other of the triggers 25-27, opening the corresponding keys 22-24, applying to the adder 29 the standards from the set 19-21, forming a pedestal different from the Xf sample not greater than

on

four

In the tick (t -} - l) i, the high-order code rewrites from triggers 8 and 9 to triggers 10 and //, generator 28 is started, trigger 32 is transferred to state T, and key 36 is opened. 39, the delay line is sampled x /, and through the adder 29 a ramp voltage of small slope, placed on a pedestal. Through the valve 33, the open trigger 32 sends pulses from the generator 42 to the trigger. Then, at one of the cycles (+ l) i, (/ + 1) n, (/ -M), keys 36-38 and sawtooth voltage (current) are opened, put on a pedestal, reaches the sampling level x, the comparator 30 is activated and returns the trigger 32 to the state "O. The valve 33 is closed, and the counter records the sampling code x, in the second and first bits.

In the cycle (/ -j-l) iv, the counter 31, the generator 28 and the triggers 19 and P. are reset. From the flip-flops 10 and and and from the counter 31, a four-digit sample code X1 is issued to the consumer via the AND 34-35 circuits.

When determining the codes of the least significant bits in cycles (), (+1) n, (t + i) m in the high-order stage, the code of the fourth and third bits of the sample xt + i is determined.

In tact (t + 2) iv the consumer receives the code

sampling X (1, etc.

Subject invention

Analog-to-digital conversion method by successively comparing signal samples with a set of saw-tooth stresses (currents) of different inclinations, for example, smooth, stepped, etc., each subsequent sample being converted to completion of the previous one, characterized in that to increase the speed quantization, the converted digital-to-analog pedestal voltage (current) of the most significant bits at the time of formation of the intermediate digits of the code is summed up with the saw-tooth voltage (current) corresponding to the defined discharge bits.

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