SU1795475A1 - Device for digital filtering on the base of discrete fourier transform - Google Patents

Description

The invention relates to digital signal processing, in particular digital filtering, based on the use of discrete Fourier transform (DFT), · h, and can be used in digital radio receivers for solving signal recognition problems, when evaluating signal parameters, while extracting useful signals on background interference.

A device for digital filtering containing a quadrature driver, analog-to-digital converters and a correction scheme for distortions caused by imperfect quadrature driver is known. The quadrature shaper consists of a set of intermediate-frequency filters connected through a switch to the signal inputs of two phase detectors, at the outputs of which low-pass filters (LPFs) are connected. As the reference voltages for phase detectors, harmonic oscillations of the frequency shifted in phase by π / 2 are used, which are equal to the average frequency of the frequency band of the input signal. At the low-pass filter outputs, in-phase and quadrature components of the complex envelope of the input signal are distinguished, of which a sequence of digital samples are formed using analog-to-digital converters (ADCs). Due to non-linearity. different channels in the slope of the amplitude characteristics, and also because of the deviation of the phase difference of the quadrature components of the OTG / 2, false signals appear at the output of the quadrature former, which limits the dynamic range.

1,795,475 A1 ί

filtered signal. To increase the dynamic range of the filtered signals, digital correction of amplitude and phase distortions is carried out. For this, in the recoding RAM and in the RAM of the phase factor included in the correction circuit, the correction function and the phase factor are respectively recorded.

The disadvantages of the known device are due to the transfer of the spectrum of the input signal to zero frequency in the analog part of the device, which leads to an increase in distortion due to zero drift, non-linear effects and to an increase in the noise level. In addition, during the operation of the mouth. Due to destabilizing factors (changes in temperature, supply voltage), values recorded in advance. the correcting function and the phase factor will not provide a complete correction of the emerging imbalances. All this leads to a limitation of the dynamic range of the filtered signal and reduces the accuracy of digital filtering. 25

The prototype of the claimed device is a DFT-based digital filtering device that contains a test signal generator, a switch, an analog quadrature driver, including 30 mixers, a local oscillator and a phase shifter at π / 2, a correction device containing an actuator in the form of four multipliers and two adders and a converter in the form of four keys, four registers and four adders, a switch: a complex number multiplier, a memory unit, an FFT processor and a digital detector. The imbalances that arise in quadrature channels are corrected. Along with the main purpose, the FFT processor is used as an imbalance sensor. the output signals of which serve as the source material from which the converter of the correction device 45 generates correction factors for the multipliers of the actuator.

In the correction mode, the inputs of the mixers are disconnected from the 50 input of the device using the switch and connected to the output of the harmonic test signal generator of the known frequency Sho + Delhi amplitude Ao; After conversion in mixers and ADCs, test signals in 55 quadrature channels have the form of discretization of the following expressions:

Xo (t) = A _o cos (AftK + yXj), Yo (t) = Ao (1. + 0a) sin (Δω t + φ _ο + δφ) \ (1) where da and δφ are the amplitude and phase imbalances in quadrature channels.

φ ₀ is the initial phase of the test signal.

The executive element passes the test signal without distortion to the input of the switch. With established unit coefficients coming from the output of the memory block, the complex number multiplier and the FFT processor implement the FFT algorithm of complex sampling (1). In the converter, the components at the frequency Δω are extracted from the real and imaginary parts of the complex signal (1) and correction factors ReF _x , ImFy, ReF _y ,, ImFx are formed, where F _x = A _o eW, F _y = -yA ₀ (1+ d _a ) _e \ (<p6 + O <p) r

In operating mode, the inputs of the mixers are connected to the input of the device. The quadrature components after correction in the actuator have the form of discretization of the following expressions:

* k (t) = χ (ΐ) · Re F _y - у (t) Re F _x , yk (t) = y (t) Im F _x - x (t) · I m F _y (2) "

The correction mode is carried out periodically with a frequency during which the amplitude-phase imbalances change slightly (usually from units to hundreds of seconds). The correction result is the absence of amplitude-phase imbalances of the quadrature channels and, as a result, suppression of mirror harmonics in the signal spectrum, which allows to increase the accuracy of digital filtering and expand the dynamic range of the device.

The prototype has the following disadvantages.

1. Limited dynamic range, which is due to the formation of a complex oscillation z ₀ (t) = x ₀ (t) + jy ₀ (x) and the transfer of its spectrum to zero frequency by the analog method using two-channel synchronous detection. Moreover, in the spectrum of Zo (x) there are spectral. components caused by zero drift. low-frequency noise of analog elements, as well as non-linear products of mixers falling into the frequency band of the converted oscillation. If Unap is the total spurious signal level in Zo (t), then the dynamic range of the device D = 20lg (Ao / U _na p) is limited due to Unap.

2. Insufficient noise immunity of filtering when processing signals of different types with different bands, due to the lack of mix i at the input of the mixers

b bandpass filters, limiting the frequency band of the processed signal. Because of the nonlinear effects of the mixers when they are exposed even to a combination of signals and noise that do not overlap in the frequency band, intermodulation noise can form that fall into the useful signal band and cannot be filtered out by the following FFT procedure. 10

3. The need to increase the performance of the Veo FFT processor while increasing the accuracy of digital filtering (increasing the resolution of digital spectral analysis), which is 15 due to the following relationship, expressed by the formula dependence

V ₆ o = γ γ log _r N (op / s), (3). ₂ θ where T _in is the duration of the sample (observation interval);

N 7 the number of samples in the sample;

d is the basis of the algorithm; 25 pbpf ~ the number of FFTs (in the simplest case pbpf = 1).

Given that T _in = N / fg, where fg is the sampling frequency, expression (3) is converted to 30

V6o “γ · log _r Ν (op / s) (4) *

An increase in resolution 35 of the digital spectral analysis is equivalent to a decrease in the frequency band Af of each of the filters of the FFT comb. Since Af ~ 1 / T _in = fg / N and an increase in resolution is associated with an increase in N, then at 40 fg = const the performance νθο should increase in proportion to log _r N under the condition that the device operates in real time. In a practical situation, Ubo’s performance is limited. 45 Therefore, there is a limit value for AfnpeA, at which a real-time mode is still provided in the device, which corresponds to a limitation of filtering accuracy. fifty

4. The impossibility of continuous digital filtering of incoming vibrations in real time, due to the need to periodically switch the device from the main $ 5 filtering mode to the auxiliary correction mode. ,

5. The complication of the special processor (SP) FFT with the introduction of the correction procedure. - imbalance of the quadrature channels, which is due to the need to operate instead of zo (t) with a complex oscillation z _K (t) = xf) + jyk (t). the bit depth of the representation f of the terms of which Gk with respect to the jth row of the representation of the terms z ₀ (t) r _bx , 'as shown in (4), is r = r _B x + 3 .;

The aim of the invention is to improve the accuracy of filtration, increase pom-i.

device resilience and provision) of a real-time mode. I

This is achieved by the fact that in the device | for disc-based digital filtering->

a Fourier transform containing a switch, an analog-to-digital converter, a complex number multiplier, a memory unit, a fast conversion unit:

Fourier transforms and a digital detector, when I the input of setting the coefficients ί of the complex multiplier is connected (to the output of the memory unit, and the outputs of the multiplier are (for complex numbers connected to the inputs of the FFT unit, the outputs of which * are connected to the inputs of the digital detector - a ra, the output of which is the output of the device, according to the proposed device, a set of analog F-band filters, a digital quadrature detector (CDD), a countdown decryptor, a cipher-clock and a clock generator are introduced, and I the first group of contacts I am connected and connected to the input of the device, the second and third groups of contacts are connected respectively to the input and output of each of the bandpass filters included in the set, the fourth group of contacts is connected and connected to the information input of the AOC, the output of which connected to input |

CKD, the first and second outputs of the CKD are connected to the first and second inputs of the decimato-I sample, the first and second outputs of which are connected respectively to the first and second inputs of the multiplier (lex numbers, the third input of the decimator of samples is connected to the output of the encoder, the inputs of which are connected to the sixth group of contacts of the switch, the fifth group of contacts of which is combined and has a potential of logical zero, the clock inputs of the ADC, CKD and the decimator of samples are connected to the first output of the clock, the second output of which oh’’s connected to the clock input of the FFT unit, which synchronizes the output of the decimator of the samples.

chen to the corresponding inputs of the multiplier;

complex numbers, memory block, block

FFT and digital detector.

On Fig, 1 presents the structure of the device; in FIG. 2 - one of the possible 'options for the structure of the CDB; in Fig.3 - a variant of the construction of the decimator samples.

The device (Fig. 1) contains a switch 1, a group of analog filters 2, an analog-to-digital converter 3, a digital quadrature detector 4, a decimator of samples 5, a multiplier of complex numbers 6, a coefficient storage unit ?, a block of fast Fourier transform 8, a digital detector 9, encoder 10. clock generator 11, first 12 (Fig. 2). second 13. third 14, fourth 15, fifth 16 and sixth 17 shift registers, the first 18, second 19, third 20 and fourth 21 adders, the first 22 and second 23 switches, the first 24. and second 25 sign formers, counter divider 26, the element EXCLUSIVE OR 27, the first 28 (Fig. 3) and the second 29

- registers, reversible pulse counter 30, amplifier-inverter 31, analog input 32 (Fig. 1) of the device, the first group of contacts 33 of the switch 1a, the second group of contacts 34 and 35 of the switch 1a, the third group of contacts 36 and 37 of the switch 16, the fourth group contacts 38 of the switch 16, the fifth 39 and the sixth 40 and 41 of the contact group of the switch 1B. input 42 CKD, first 43 and second 44 outputs of CKD, third input 45 of the decimator of samples, the first 46 and second 47 outputs of the decimator of samples, the input of the coefficients of the multiplier of complex numbers 48, the first 49 and second 50 outputs of the multiplier of complex numbers, the first 51 and second 52 FFT block outputs, device output 53, clock input 54 CKD, clock input 55 of the decimator of samples, synchronizing output 56 of the decimator of samples, outputs of the second 57 (Fig. 2), third 58. fourth 59 and sixth 60 shift registers, first 61 and second 62 counter divider outputs, output 63 of the circuit EXCLUDING JUST OR. ·

After passing through the corresponding band-pass filter from set 2, the signal at the input of the ADC 3 can be represented as follows:

x (t) = A (t) cos [b'Y - </ ED] = = A _c (t) cos Plot + As (t) sin PJot, (5) where A _c (t) = A (t) COS φ (t);

A _s (t) = Aft) sinw (t);

A (t) - signal amplitude:

y / t) is the phase of the signal;

(Oo is the central circular frequency; t is the current time;

A _s (t) is the sine quadrature component;

A _c (t) is the cosine quadrature component.

In accordance with the Kotelnikov theorem, signal (5) can be represented by discrete samples x (t _n ) = x (n). where t _n = ηΔί, η -, 1,2 ..... if you select the sampling interval from the condition

At <1 / AF, (6) ¹⁰ where ΔΕ is the frequency band occupied by the signal x (t).

Digital algorithms for calculating the quadrature components of the signal A _s (n) and A _c (n) 15 and the structure of the digital 'quadrature detector are known. If you select a sampling interval from the condition

Δΐ = π / 2ω ₀ , (7) then according to the seven current samples of the signal x (n), x (n-1), x (n-2), x (n-W), x (n-4), x (p-5), x (p-6), you can calculate the Hilbert-converted sample of the signal, referred to the moment of time (n-3) according to the formula

2g (n -3) = 1.125 [x (l-4) - x (n-2)] + 0.125 [x (n-6) -x (n)] (8)

In even measures n = 2m, m = 0,1,2, ... 30 values of quadrature components are calculated

A _c (2m) = (-1) ^t * x (2t);

A _s (2m) = (-1) ^{t + 1} x _g (2t) (9) in odd cycles with n = 2rn-i-1, m = 0,1,2, ... the values of the quadrature components are calculated as

A _c (2m + 1) = (-1) ^m · x _g (2t <-1):

A _s (2m + 1) = (-1) ^m x (2m + 1) (10)

Thus, when choosing the sampling interval in accordance with expression (7), finding the sine and cosine quadrature components is reduced to 45 switching with the corresponding sign according to expressions (9) and (10) of the values of the digitized samples of the signal x (n) and calculated according to the expression ( 8) the corresponding time values of the pre-formed by Hilbert samples x ₍ (p). With this method of forming samples of complex oscillations, when quadrature detection, including the formation of complex oscillations and transfer from 55 of its spectrum to the zero frequency, it is carried out by a single-channel digital circuit, there is no need to introduce correction, in addition, the spectral components caused by the zero drift and i ί f

• low-frequency noise of analog elements are shifted along the frequency axis and do not fall into the frequency band of the complex envelope A (t) = A _c (t) + jAs (t). We note that the specific relation for calculating xi (n) depends on the properties of the signal x (x) and the required conversion accuracy. The above relation (8) provides an accuracy of 0.1% in the relative frequency band ± 17% and 1% 10% in the relative frequency band ± 30%. that with the appropriate choice of bit depth, the ADC can provide the dynamic range of the device, respectively, 60 and 40; db Moreover, the conversion error has 15 monotonic dependence on the detuning.

Thus, due to the presence of a _g digital quadrature detector, prerequisites for enhancement are provided. • noise immunity of digital filtering 20 by increasing the dynamic range of the device and • transferring the frequency of the spurious signal spectral components to the inoperative region.

Condition (7) for choosing the sampling interval is more stringent compared to sufficient condition (6) and, moreover, it is not directly related to the frequency band AF of the signal x (t). As a rule, in real devices, ω ₀ = const, therefore, with a decrease in the frequency band of the AF signal, the discrete samples A _c (n) and A _s (n) following the interval At selected from condition (7) are excessive represent the signal x (t). For decimation of samples, it is thinning I times, so 35 that the reduced sampling interval is At _p = lAt, and if condition (6) is fulfilled for Δΐ _ρ , the representation of the original signal is accurate. x (t), as is known. . · Does not worsen. Thanks to the introduction of decimation of samples while limiting the frequency band of the input signal by connecting the corresponding band-pass filter from set 2, it becomes possible to increase the accuracy of digital filtering without increasing the performance of the FFT block.

Unlike the prototype, in the proposed device, the number of samples in the sample is fixed N = const, and the reduced value 50 of the sampling rate is after decimation f _gp = f _g / l. Therefore, the required performance of the FFT processor even decreases according to expression (4) while increasing the resolution 55 of the digital spectral analysis Af = Af _gp / N.

A device for digital filtering based on DFT operates as follows. In accordance with the type of 'signal · ’y (t). subject to filtering, the i position of switch 1 is selected as follows. so that the frequency band occupied by the signal is most consistent with the bandwidth of one of the filters in set 2.ί

The analog signal y (t) from the input of the device 32 through the first 33 and second 34, 35 of the contact group of switch 1 is input to the selected k-th filter from group 2. The signal x limited in band in accordance with the amplitude-frequency characteristic of the k-th filter (t) through the third 36.37 and fourth 38 of the contact group of the switch 1 is input;

LTSPZ. At the same time, in accordance with the position of switch 1, a position code is present at the input of cipher-j of torus 10, according to which a binary code is generated at the output of cipher 10, which unambiguously determines J the decimation coefficient of readings I.f

Using ADCS, the signal x (t) is represented by;

is encoded by the samples x (nA t), ηI = 1,2, .. ,, following the interval of disc-Atization At, the duration of which is chosen?

on according to the expression (7). Corresponding sequence of impulses?

It is fed to the clock at the ADC from the first output of the clock generator 11.

The sequence of samples x (nAt) is fed to input 42 of CDD4.

Digital quadrature detector (FIG.

2) contains in series the first 12, second 13, third 14, fourth 15, fifth 16 and sixth 17 registers, as well as the first 18, second 19, third 20 and fourth 21 adders, switches 2 2 and 23. first 24 and second 26 shapers of the sign, counter-divider 26 and element 27, the information input of the first register 12 is connected to the input 42 of the CDD, as well as to the first input of the adder 19, to the second input of which the output 60 of the register 17 is connected, the outputs 57 of the register 13 and 59 of the register 15 are connected respectively to the first and second inputs of the adder 18, the output of which is connected to to the input inputs of the adders 20 and 21, the output of the adder 19 is connected to the second input of the adder 20, the output of which is connected to the second input of the adder 21, the output 58 of the register 14 is connected to the first input of the CMM-. j of the switch 22 and the second input of the switch 23. The output of the adder 21 is connected to the second input of the switch 22 and to the first input of the switch 23. The outputs of the switches 22 and are connected respectively to the inputs of the driver 24 and 25, the outputs of which are connected respectively to the outputs 43 and 44, the clock input 54 is connected to the clock inputs of the registers 12 to 17 and to the clock input of the counter-divider 26, the first output is 6! which is connected to the clock inputs of the switches 22 and 23 and to the first input of the element EXCLUSIVE 5 OR 27, the second output 62 of the counter-divider 26 is connected to the second input of the element 27 and to the control input of the sign former 25, and the output 63 of the element 27 is connected to the control input of the former sign 10 ka 24,

Consider the steady state operation of CDD4. In the shift registers 12-17, the values of six samples of the ADCS are recorded: -respectively, in the register 12 - x (l-1), in the register 15 - 13 - x (p-2) and so on up to the register 17 - x (n- 6). Given the current output value of the ADCS x (p), the calculation of 2xg (p-3) in accordance with formula (8) is as follows. For simplicity we denote 20 x (p-t) = x (t), where r is the delay, m = 0.6.

Expression (8) is equivalent to the representation

2xr (3) = [x (4) - x (2)] + 0.125 {[x (4) - x (2)] + 25 (x (b) -x (O)])

Subtraction of samples x (4) - x (2) generated at outputs 59 and 57 is performed by adder 18, and subtraction of samples x (6) - x (0) generated at output 60 and input 42, 30 is performed by adder 19. In the adder 20, the two differences are added, presented in braces. The transfer of the output value of the adder 20 to the input • of the adder 21 is performed with a shift of 3 35 binary digits, which corresponds to a multiplication of 2 ' ³ . Using the adder 21 calculates the value. 2xg (3), which is transmitted to the second input of the switch 22 and the first input of the switch 23 with a shift of 40 by one bit, which corresponds to division by 2. At the same time, the value x is supplied to the first input of the switch 22 and the second input of the switch 23 from the output 58 of the register 14 ( 3). 45

The clock-wise shift of the values of the readings x (n) is carried out using a sequence of pulses of frequency f _g supplied to the clock input 54 of CDD4, FIG. 4a shows a sequence of pulses of 50 frequency frequencies. f _g . which is fed to the input of the counter-divider 26.-On the first output 61 of the counter 26, a meander frequency fg / 2 is produced, shown in FIG. 46. A sequence of pulses of frequency fg / 2, 55 supplied to the clock inputs of switches 2 and 23, controls the passage of samples x (n) and xg (n) on the outputs of the switches.

From the outputs of switches 22 and 23, the corresponding values of the samples come from?

to the inputs of the formers of the sign 24 and 25.ι

Shaper operation control 25 osu | there is a meander sequentially.;

frequency fg / 4 - FIG. 4c, formed on the second output 62 of the counter-divider 26 and ’arriving at the control input formmi- | rover 25.

The control sequence for the character driver 24 is formed from 'sequences of frequencies fg / 2 and fg / 4 s.

using the EXCLUSIVE OR j element

27. Formed sequence | (Fig. 4d) is fed from the output 63 of the element 27 * to the control input of the shaper 24. V.>

In accordance with the control sequences for the sign formers, multiplication of readings by (-1) ^m and »(-1) ^{m + 1 is} carried out according to formulas (9) and (10).

In the table. 1 shows the current values of j in-phase Ac and quadrature readout | A _s at outputs 43 and 44, taking into account the i sequences shown in FIG. 46, c, d, and numbering of frequency pulses | Sampling for eight measures. ί

From the first 43 and second 44 outputs of the CDD, the samples Ac (p) and A _s (n) at a rate determined by where / arrive at the first and second inputs ¹ 'of the decimator of samples 5 (Fig. 2). The decimator of samples 5 (Fig. 3) contains the first 28 and second 29 registers, a reversible pulse counter 30 and an amplifier-inverter 31, D inputs of a reversible counter 30 are connected to the third input 45 of the decimator, an input

-1 counter 30 is connected to the clock input 55 of the decimator, the output of the reverse counter-counter 0 is connected to its recording input, | the clock inputs of the registers 28 and 29 and the input '· of the amplifier-inverter 31, the output of which 56 is connected to the synchronizing output · of the decimator, and the outputs of the registers 28 and 29>

connected to the outputs 46 and 47 of the decimator. | At the input 45 of the decimator 5 there is a decimation code coming from the output | encoder 10. At the clock input 55 decima | torus from the clock generator 11 po!

pulses of frequency fg step in. The samples Ac (l) and A _s (n) are recorded in the registers 28 and 29 by the pulses generated at the output "<0 of the counter 30. These pulses are generated when the number.

received at the input of 55 pulses of frequency fg is equal to the number corresponding to the decimation code. At the same time, with these pulses each time, a ¹ write ^of the decimation code in counter 30 is performed.

Through the amplifier-inverter 31, the thinned pulses corresponding to the new 13th value of the sampling frequency f _gp = fg / l are fed to the output 56 of the decimator 5.

The decimated sequences A _s (y) and A _s (y), where γ = 0,1,2 ..... from the outputs 46 and 47 of the decimator 5 are fed to the first and second inputs of the multiplier of complex numbers 6, The input 48, the coefficients of the multiplier 6 are set from the memory unit 7; the coefficients of the weight function are received - the function is WO '). In the multiplier 6 is weighted 10 processing:

And _in (y) = W (y) [A _c (y) + JA _s (y)]

Weighted real A _C in (p) = A _c (y) W (y) and imaginary A _SB (>) = A _s (y) W (y) sequences of samples from outputs 49 and 50 of multiplier 6 are fed to the first and second inputs BPF8 unit. The synchronization of the operation 20 of the multiplier 6 and block 7 is carried out using a sequence of frequency fgp coming from the output 56 of the decimator 5 to the corresponding synchronization inputs.

The BPF8 block implements in a real 25 time scale the well-known discrete Fourier transform algorithm:

Βξ = Σ ¹ [Asb (/) + '30 y- ° · + J Azv (y)] · exp (- ~ y £), where ξ is the index of the spectral components, £ = 0.14-1.

To ensure the operation of the BPF8 unit, a clock sequence of pulses with a frequency f _T is supplied to its clock input from a clock generator. 40

At the end of the calculations for the next sample of samples, the real ReB £ and imaginary ΐΓπΒξ components of the spectrum are coupled from outputs 51 and 52 of the FFT8 block to the inputs of digital detector 9.

In the digital detector 9 are calculated. power spectrum components according to the expression:

Βξ · Βξ * = (Re Βξ) ² + (lm B £) ² . (11) where Βξ is the complex conjugate component of the spectrum, or the components of the amplitude-55 spectrum according to the expression:

/ B £ / = ^ (ReB £) ² + (lm Βξ) ² , ξ = Ο, Ν - 1

The values of the spectrum components calculated by the digital detector are transmitted to the output 53 of the device.

The digital filtering device can be performed on a modern element base. As a group of 2 filters, it is advisable to use analog bandpass filters used in radio receivers of the corresponding wavelength range. For example, to filter the signals of the decameter wavelength range of the filters of the P399A radio receiver, electromechanical filters are made up of a passband of 3 dB, respectively 10.6.3.1 and 0.3 kHz.

ATSPZ can be performed on the basis of commercially available chips of a 6-bit high-speed ADC of the type 1107PV1 and 8-bit 1107PV2. As the shift registers 12-17 CKD4 (Fig. 2), you can use the chip 533 IR23, 533 IR27,1804IR2. Adders 18-21 can be implemented on arithmetic logic device (ALU) circuits of type 533IPZ and accelerated transfer scheme 533IP4. Since these adders constantly perform the same operation, the operation code is hard-coded to the ALU control inputs. It is convenient to implement multiplexers on microchips of the 533KP11, 533KP16 type. In this case, the sequence shown in FIG. 46.

Shapers sign 24.25 (Fig. 2) can be performed on ALU chips type 53314-3. In this case, the number 0.3 is set at the inputs 0.3-3.0, and the inputs 0.1-3.1 are connected to the outputs of the switches 22,23. Code combinations are provided to the control inputs SE, which are formed from the sequences shown in FIG. 4c and 4d. Then, the input number is transmitted to the ALU output without changing the sign, which corresponds to the arithmetic operation 0 + B, where B is the input state is 0.1-3.1, and the number is with the sign inversion, which corresponds to the 0-B arithmetic operation.

The counter-divider 26 can be performed on the chip 533IE5, and the element EXCLUSIVE OR 27 on the chip 533LP5.

Registers 28. 29 of the decimator of samples (Fig. 3) are conveniently performed on microcircuits of the type 533IR23, 533IR27, 1804IR2, with a reversible counter 30 on the chip 533IE7.

Block 7 (Fig. 1) can be performed on ROM chips, for example, 556РТ4, 555РТ5, t

I

J

556РТ7, and the multiplier of complex numbers 6 on chips like 18O2VRZ, 1802VR4.

Taking into account the necessary speed, it is advisable to perform the BRF9 unit in the form of a specialized FFT processor, 5 implemented on hard logic or on microprocessors.

Digital detector 9. realizing the calculated power spectrum according to (11) can be performed on microchip-10 resident 1802ВРЗ, 1802ВР4 and ALU 533IPZ.

When the detector 9 implements expressions (12), the multipliers and ALU must be supplemented by the square root calculator. The latter is conveniently implemented on the basis of ROM. 15 The encoder 10 can also be implemented on the basis of ROM, or on functional elements OR.

Clock generator 11 includes a frequency stabilized quartz resonator 20 • rum frequency generator fr and a frequency divider that generates pulses with a repetition rate fg and can be implemented on 533 series microcircuits. 25

Thus, thanks to the totality of the nodes introduced into the prototype, the objective of the invention is achieved. At the same time, the increase in filtering accuracy is caused, on the one hand, by the possibility of 30 increasing the resolution of spectral analysis, which is ensured by the introduction of a decimator of samples and a set of band-pass filters, and, on the other hand, by an increase in noise immunity, i.e. by reducing the level of false signals in the analyzed frequency band, which is ensured by · replacing the analog quadrature shaper with a digital quadrature detector and also introducing a set of bandpass filters.

Replacement of the analog quadrature shaper, when using which a correction mode is necessary, allows implementing the continuous real-time mode in the claimed device 45, as well as abandoning the increased requirements for the FFT block in terms of the bitness of the representation of numbers.

The 50 Proton Central Design Bureau has implemented a digital device mockup. filtering using a set of bandpass filters of a commercially available P-399A radio receiver with frequency bands ΔΦ: 10.6, 3, 1 and 55 0.3 kHz. The squareness of the amplitude-frequency characteristics of the filters at a minus 50 dB level was at least 3. The value of the last industrial frequency f _o = 15 kHz, therefore, in accordance with (7) f _g = 60 kHz.

The procedure of digital spectral analysis was performed on a special DFT processor, in which at N = 512 and f _T = 4.8 MHz the processing mode · in real time was provided. In the table. 2 shows the relationship of the parameters in the digital filtering device and the required performance calculated by the formula (4) at r = 2. The last column shows the required values of the FFT unit performance in the prototype when implementing spectral analysis with increased accuracy.

The data table. 2 show that with the used bandpass filter group and the decimation coefficients selected, the filtering accuracy can be increased by 30 times without increasing the FFT processor performance. Improving the filtering accuracy in the prototype is associated with the need to increase the dimension of the sample N (up to 30 times), complicate the nodes of the FFT unit and increase its productivity by 1.5 times.

In FIG. 5 illustrates the effect of the decimation procedure on the location of the main spectrum module / B (f) / and its mappings on the frequency axis. In FIG. 5a shows the conditional signal spectrum taking into account the rectangularity of the band-pass filter ΔΦ = 10 kHz present at the ADC input.

In FIG. 56 shows / B (f) / at the ADC output after sampling f _g = 60 kHz. The appearance of inverse mappings is characteristic. As a result of quadrature detection, the main display is shifted to zero frequency and the inverse mappings disappear, as shown in FIG. 5c. In this case, the low-frequency components of noise of analog origin B pairs are shifted to the inactive frequency region, as shown in FIG. 5c.

In FIG. 5a shows the / V mappings (0 / with a filter bandwidth ΔΦ = 3 kHz, and Fig. 5e shows the position of mappings after decimation with a decimation coefficient I = 3; since the spectra of mappings after decimation do not overlap; as a result of the decimation decimation procedure in the spectrum of the analyzed signal does not occur.

If we characterize the noise immunity by the dynamic range of representation of the spectrum components, then in the prototype D is determined by the identity of the quadrature channels. As follows from the table. 1.3. to achieve D = 40 dB, the deviation of the amplitude characteristics from ideal should not be

|

I

G c

> i i I ί

Thus, in the proposed device, digital filtering based on *

DFT compared with the prototype provides improved filtering accuracy without фильтрации increase at the same time productivity | processor, which allows you to implement a filtering mode in real time, and also increases noise immunity-I

PURITY.I

10 · exceed 1%, and the phase difference should not exceed I. Even taking into account the correction introduced in the prototype, such an identity is difficult to achieve in the frequency band. In the proposed device, highly accurate quadrature components are formed and the dynamic range is limited by the bit depth of the used ADC (5). For example, for an 8-bit ADC, D ~ b '· B = 48 dB.

Claims (4)

The claims 1 A device for digital filtering / • based on a discrete Fourier transform, containing a switch, an analog-to-digital converter, a multiplier ’of complex numbers, a coefficient storage unit 2 cents, a fast Fourier transform unit and a digital detector, the input of setting the coefficients of the complex number multiplier connected to the output of the coefficient storage unit, and the outputs of the multiplier 2 complex numbers connected to the inputs of the fast Fourier transform unit, the outputs of which are connected to the inputs of the digital detector, output which is the output of the device 3 further, in order to increase filtering accuracy, a group of analog bandpass filters, a digital quadrature detector, a decimator of samples, an encoder and a clock generator are introduced into it, the first · group of switch contacts connected to the input of the device, the second and the third group of contacts are connected respectively to the input and output of each of the analog bandpass filters of the group, the fourth group of contacts is connected to the information input of an analog-to-digital converter, the output of which is connected to the input of qi rovogo quadrature detector, the first and second outputs of the digital quadrature detector are connected respectively to the first and second information vhodam.detsimatora O counts, the first and second information outputs of which are respectively connected to first and second inputs of the multiplier operands complex numbers. 5, the third information input of the decimator of the samples is connected to the output of the encoder, the inputs of which are connected to the fifth group, the contacts of the switch, the sixth group of contacts of which is connected to the logical zero bus of the device, the clock inputs of the analog-to-digital converter, digital quadrature detector and decimator of samples are connected to the first the output of the clock generator, the second output of which is connected to the clock input of the fast Fourier transform unit, the synchronizing output of the sample decimator is connected to named inputs of the complex number multiplier, On the coefficient storage unit, the fast Fourier transform unit, and the digital detector. '' Table 1 m δ ι 2 3 η 0 1 2 3 4 5 6 7 A _c (n) Xo ^χ Μ - Χ2 -HGZ X4 Xg5 - xb -Hg7 L-.ZW’lL ...., - Xro X1  Xg2 - xs - xg4 X5 Hgb -X7 19 1795475 ’* 20 table 2 Filter strip ΔΦ, kHz Coef., Decimatz, I The lead. sampling rate, fflp. kHz Duration, output T _in , ms Dist. between components DG.Hz Produces, Ubo -10 ⁵ processor claimed U-80 prototype 10 1 60 8.53 117.2 2.7 2.7 6 2 ³⁰ . 17.06 58.6 1.35 3.0 ³ 3 20 25.6 39.1 0.9 3.18 1 10 6 85.3 11.7 0.27 3.7 0.3 thirty 2 256 3.9 0.09 4.17 f I i i f I ί i I I ί I I ί Fig 2 Fig! . Γ ~~ Ί ____ I --- ~ L _______ G ~ —I 4з_Γ ~~ 1_ I - L_Г -] ___ Г ~ Fig. H