SU1762399A1 - Switch - Google Patents

Abstract

The essence of the invention: the device contains: 5 transistors, 6 resistors, 1 trigger, 1 input bus. 2 bus output, 1 shared bus. 1 il.

Description

The invention relates to a pulse technique.

Known switch containing the first transistor, the emitter and collector which is respectively connected to the input and the first output bus, the base is connected to the first output of the first resistor, the second resistor and the second output bus.

The aim of the invention is to expand the field of use by providing even numbers on the first output bus and odd input pulses on the output bus without distorting their durations and amplitudes.

This goal is achieved by the fact that in the switch containing the first transistor, the emitter and collector of which are connected respectively to the input and the first output bus, the base is connected to the first output of the first resistor, the second resistor and the second output bus, the second, third, fourth and fifth transistors, third, fourth, fifth and sixth resistors and a trigger, the output of which through the second resistor is connected to the base of the second transistor, to the first output of the third resistor and to the collector of the third transistor, whose base is The fourth resistor is connected to the second output bus, to the trigger start input, the reset input of which is connected to the second output of the third resistor and to the first output bus, and to the collector of the fourth transistor whose emitter is connected to the input bus and to the emitter of the fifth transistor whose base through the fifth resistor is connected to the second output of the first resistor and to the collector of the second transistor, the emitter of which is connected to the emitter of the third transistor, to the common bus and through the sixth resistor to the base of the fourth tra ican and to the collector of said fifth transistor.

The invention is illustrated in the drawing, which shows transistors 1-5, resistors 6-11, trigger 12. input bus 13, output buses 14 and 15, common bus 16.

Transistors 1. 4 and 5 of one type of conductivity, and the remaining transistors of another type of conductivity (2 and 3).

Suppose trigger 12 is in a position where a high potential at its output, with which transistor 2 is saturated through resistor 7. When a pulse arrives at the input bus 13, transistors 1 and 5 will saturate along the following lines: emitter - base of transistor 1 (L

with

4 Pts

yu yu yu

a resistor 6, a collector-emitter of a saturated transistor 2, and a common bus and a circuit: emitter — base of the transistor 5. resistor 10, a collector-emitter of a saturated transistor 2 and common bus 16. In this connection, an input pulse is formed on the collectors of transistors 5 and 1 The voltage on the collector of the transistor 5 is securely closed by the transistor 4, the voltage on the collector of the transistors 1 is output on the bus 14 output. With this voltage, the transistor 2 is saturated with the current of the resistor 8 and the input translates the trigger 12 into a state in which there is no voltage at its output. With the formation of the trailing edge of the input pulse UBX on the bus 13, the trailing edge of the output pulse Ovix1 is formed on the bus 14. With the arrival

the next input pulse UBx, the transistor 4 saturates along the circuit: voltage source UBX, bus 13, the emitter is the base of transistor 4, resistor 11 and common bus 16. On the collector of transistor 4, the leading edge of the output pulse I / O 2 is formed on bus 15 from which saturation occurs the transistor 3 by the current of the resistor 9 and the setting of the trigger 12 to the initial state, in which its voltage is high. The saturated transistor 3 securely holds in the closed-. In this state, the transistor 2 until the formation of the falling edge of the output pulse and the output 2 on the bus 15, which occurs at the time of the formation of the falling edge of the input pulse UBX on the bus 13. After that, the device returns to its original state and then works similarly as before.

Thus, the considered switch alternately connects the input pulses to the first, then to the second output bus, on which the input pulses are allocated that are not distorted both in the long-term and amplitude, which expands its range of use. If the voltage from trigger output 12 is used as the output voltage, then this switch can be used as a counting trigger in which no capacitors are used and which is operated by input pulses of any duration. This also expands the range of use of this switch.

Claims (1)

The invention of the switch containing the first the transistor, the emitter and collector of which are connected respectively to the input and the first output bus, the base is connected to the first output of the first resistor, the second resistor and the second output bus, differing in that, in order to expand the field of use, a second, third, the fourth and fifth transistors, the third, fourth, fifth and sixth resistors and a trigger, the inverse output of which through the second resistor is connected to the base of the second transistor, to the first output of the third resistor and to the collector of the third transistor, otorrhea through a fourth resistor connected to the second output bus, with the trigger start input, the reset input of which is connected to the second output of the third resistor and to the first output bus, and to the collector of the fourth transistor, the emitter of which is connected to input bus and with the emitter of the py transistor, whose base through the fifth resistor is connected to the second output of the first resistor and to the collector of the second transistor, whose emitter is connected to the emitter of the third transistor, to the common bus and through the sixth resistor to the base of the fourth transistor and to the collector n that transistor.