SU1758891A1 - Device for discrete information transfer - Google Patents

Abstract

SUMMARY OF THE INVENTION: The device comprises a clock pulse generator 1, a HE element 2, AND-HE elements 3 and 4, switches 5 and 6, transformers 7 and 8, diodes 9-12, capacitors 13 and 17, resistor 14, power supply bus 15, variable resistor 16. 1 Il.

Description

The invention relates to communication technology and can be used in systems for transmitting discrete information by bipolar signals through a two-wire line with galvanic isolation.

The purpose of the invention is to increase the speed of information transfer.

The drawing shows a structural electrical diagram of the device.

The device contains a clock generator 1, a HE 2 element, a first 3 and a second 4 NAND elements, a first 5 and a second 6 keys, first 7 and a second 8 transformers, the first 9, the second 10, the third 11 and the fourth 12 diodes, the first capacitor 13, a resistor 14, a power bus 15, a variable resistor 16, and a second capacitor 17.

The device operates as follows.

The input binary signal is supplied to the AND-NOT 3 element, and through the inverter NOT 2 to the AND-NOT 4 element, where it modulates a sequence of clock pulses with a duty cycle of two supplied from the generator 1 to the first inputs of the AND-NOT 3,4 elements.

With a high level of the input signal from the output of the AND-NOT 3 element, a series of clock pulses is issued through the key 5 to the primary winding of the transformer 7. From the first half of the secondary winding of the transformer 7 through the diode 9, a series of clock pulses of positive polarity is fed to the output of the device.

After transmission of each clock pulse of the series through transformer 7 and closing of the key 5 from the second half of the secondary winding of transformer 7 through diode 10, an additional pulse of positive polarity is generated at the output of the device, which is generated by the energy stored by the transformer 7 when the clock pulse passes through it. Form. In this way, the pulses form an additional series of pulses shifted relative to the series of clock pulses by the value of the duration of the clock pulse.

At the output of the device, the pulse amplitudes of both series differ insignificantly, and the pulse duration of the additional series provides filling in the intervals between the pulses of the clock series, which is determined by the operation mode of the transformer (primary winding current, clock repetition rate, etc.). When the pulses of both series are added at the output of the device, a signal of positive polarity corresponding to the duration of the input signal of a high level will be generated.

The capacitor 13 smooths out the pulsations and high-frequency surges that can occur at the junction of the edges of the pulses of both series, and forms a flat top of the output signal, the resistor 14 matches the output of the device with the communication line.

When the input device high level binary signal to low the output of a series of pulses from the element AND 3 stops and the series of pulses of the clock frequency begins to arrive from the output of the element And N. 4 through the key 6 to the primary winding of the transformer 8. From the first half of the secondary windings of transformer 8 through diode 11 and from the second half of the secondary winding of transformer 8 through diode 12, pulses of positive polarity of the clock series and additional series generated by the energy stored by transformer 8 are fed to device progress. Since the secondary windings of transformers 7 and 8 are connected to the output of the device in antiphase, the signals from the transformer 8 will recharge the capacitor 13 and generate a negative polarity signal at the device output that corresponds to a low-level signal of a low level at the device input.

Thus, in accordance with changes in the input signal level, a series of clock pulses will be issued alternately in antiphase from transformers 7 and 8 together with a series of additional pulses, from which a bipolar signal corresponding to the input signal will be generated at the output of the device.

Diodes 9, 10, 11, 12 provide the formation of the amplitude of the output signal.

The variable resistor 16 sets the operation mode of the transformers 7, 8 and in insignificant limits the amplitude of the output signal is regulated. The capacitor 17 provides a reduction in the recharge time of the capacitor 13 when the polarity of the output signal changes.

Claims (1)

Claim A device for transmitting discrete information, containing a clock generator, the output of which is connected to the first inputs of the first and second NAND elements, the outputs of which are connected to the inputs of the first and second keys, respectively, two diodes, the first capacitor, the first and second outputs of which are connected respectively to the first and second terminals of the resistor, a variable resistor, a second capacitor and a first transformer, the first terminal of the primary winding of which is connected to the output of the first key, an element HЁ, the output of which is connected It is connected with the second input of the second AND-NOT element, while the second input of the first AND-NOT element is connected to the input of the element NOT and is the input of the device, the output of which is the first and second conclusions of the resistor 10, characterized in that, with In order to increase the information transfer rate, the third and fourth diodes and a second transformer were introduced, the first output of the primary winding of which is connected to the first 15 output of the second capacitor, to the first output of the variable resistor and to the second output of the primary winding of the first transformer, the first and second the second terminals of the secondary winding of which are connected to the anodes of the first and second diodes, respectively, whose cathodes are connected to the middle terminal of the secondary winding of the second transformer and to the first output of the resistor, the second terminal of which is connected to the middle terminal of the secondary winding of the first transformer and to the cathodes of the third and fourth diodes, the anodes of which are connected respectively to the first and second terminals of the secondary winding of the second transformer, the second terminal of the primary winding of which is connected to the output of the second switch, when m second terminal of the second capacitor and the second and third terminals of the variable resistor coupled to the power bus.