SU1757117A1 - Device for binary information transfer - Google Patents

Abstract

FIELD OF THE INVENTION The invention relates to improving the noise immunity of a device. The device for transmitting binary information contains Mr. 1, El I 2, T-flip-flop 3, register 4 shift, DAC 5, adders 6 and 14 modulo two, comparators 7 and 11, integrator 8, D-triggers 9 and 15, a full-wave rectifier 10 pin delay 12 and an adder 13. The goal is achieved by suppressing the low-frequency components in the spectrum of a linear transmitted signal. 2 Il.

Description

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The invention relates to communication technology and can be used for transmitting digital signals in systems with pulse code modulation.

The circuit of the invention is to increase the noise immunity of the device by suppressing the low-frequency components in the spectrum of the linear transmitted signal.

FIG. Figure 1 shows the structural electrical circuit of the proposed device; Fig. 2 shows stress plots showing his work.

The device for transmitting binary information contains a generator 1, an element of AND 2. A T-flip-flop 3, a 4-shift register, a D / A converter 5, a first modulo two b, a first comparator, integrator V, a D-flip-flop 9, a two-half-period rectifier the driver 10, the second comparator 11, the delay line 12, the adder 13, the second adder 14 modulo two and the second D-flip-flop 15.

The device works as follows.

At the first input of the device, an information signal is received in the NRZ format of the m BIPIC type obtained by adding two additional bits to each m information bits - the P bit and C bit (FIG. 2a). Logical zero level is recorded at the P bit position. information about telecontrol, office communication, sync group. In this case, two additional bits are added for every ten information bits (Fig. 2a). Next, the digital signal is fed to the second input of the element 1/1 2, the first input of which receives the clock frequency (Fig. 2b), as a result of which the output of the And 2 element produces a stream of pulses (Fig. 2d) corresponding to the logical units of the incoming to the first input of a digital signal device. The pulses are fed to the input of the T-flip-flop 3, the output of which receives a signal (Fig. 2e), which is fed to the D-input of the shift register 4, to the C-input of which the clock frequency is supplied from the output of the generator 1. The shift register 4 is designed to convert digital signal, arriving at its D-input, from a serial code to a parallel one; From the first, second (m + 2) -ro outputs of the register 4 shift digital signals

arrive at first, second (t + 2) th

the inputs of the digital-to-analog converter 5, which is designed to convert a digital signal to an analog one and from whose output the signal in analog form is fed to the second input of the first comparator 7.

At the output of the first switch 7, a signal is received (Fig. 2e) —a digital group sum code indicating how many units are in a group of pulses per (t + 2) bit — more than half or less than or equal to half of the pulses from (t + 2) bits. At the first input of the first comparator 7, a constant voltage is applied to the second input of the device, corresponding to the case when the number of logical units in a pack of (t + 2) bits is 1/2 (t + 2).

Next, the signal (Fig 2d) - the code of the digital sum of the group arrives at the D input of the first D flip-flop 9, to the C input of which the frequency is fed (Fig. 2b) is equal to fT / (m + 2). The first D-flip-flop 9 is designed to store the group's digital sum code entering its D-input for (rp + 2) cycles and forms a signal at its output (Fig. 2ri) - a group's digital sum code indicating the number of information logical units. in a group of (t + 2) bits. Next, the code of the digital group of the sum (Fig. 2h) is fed to the first input of the second adder 14 modulo two. the second input of which receives the code of the current digital sum, formed by the second comparator 11. Adding modulo two signals passing to the input, the second modulator 14 modulo two generates a signal (Fig. 21} inversion or no signal inversion (Fig. 2f), arriving at the first input of the first adder b modulo two, depending on the ratio of the digital sum code of the group and the code of the current digital sum.The inversion signal is then fed to the D input of the second D flip-flop 15, the C input of which receives frequency B is equal to fT / (m + 2).

The second D-flip-flop 15 is designed to store the inversion signal arriving at its D-input, or the lack of it for (t + 2) cycles. Then the inversion signal (Fig. 2k) is fed to the second input of the first adder 6 modulo two, the first input of which receives a signal (Fig. 2f). At the output of the first adder 6 modulo two, a signal is formed (Fig. 2q), which is an inverse (or direct) signal (Fig. 21) and fed to the input of the integrator 8, which is intended to store information about the current digital sum of the digital signal, incoming at his entrance. From the output of the integrator 8, information about the current digital sum arrives at the first input of the second comparator 11, the output of which forms the code of the current digital sum (Fig. 2n), showing the ratio of logical units and zeros of the information signal. To the second input of the second jtOMnapaTopa 11 from the third input of the device

a constant voltage is applied corresponding to the case when the number of logical ones and zeros in the signal supplied to the input of the integrator 8 is equal to. From the output of the second comparator 11, the code of the current digital sum (Fig. 2n) is fed to the second input of the second adder 14 modulo two.

From the output of the first adder 6, the modulo two digital signal (Fig. 2q) is fed to the input of the adder 13 and to the input of the delay line 12, the output of which produces a signal (Fig. 2d), fed to the first input of the adder 13, the output of which forms a two-level the signal (Fig. 2s), incidentally in two times smaller band, the Two-level signal (Fig. 2s), the passage through the full-wave rectifier 10, is converted into the original digital signal (Fig. 2t), and the telecontrol information zi, the sync group (bits C) remains as it was at the transmitting side, and bits P undergoes changes in signal processing. But this does not affect the transmission of basic information symbols.

Claims (1)

Apparatus of the Invention A device for transmitting binary information, comprising a generator connected in series, an AND element, the second input of which is the first input of the device, and a T-flip-flop and a series-connected delay line, an adder, to the second input of which a delay line input is connected, and a full-wave rectifier The output of which is the output of the device, characterized in that. that, in order to improve the noise immunity of the device by suppressing the low-frequency components in the spectrum of a linear transmitted signal, a shift register, a serially connected D / A converter, a first comparator, the second input of which is the second input of the device, and a first D-trigger and serially connected first are entered sum modulo two, integrator, second comparator, the second input of which is the third input of the device, second modulo two. the second input of which is connected to the output of the first D-flip-flop, and the second D-flip-flop, the output of which is connected to the second input of the first modulo-two adder, the first input of which is connected to the corresponding output of the shift register, whose D- and C-inputs are connected respectively to the output T-flip-flop and with the first output of the generator, the second output of which is connected to the C-inputs of the first and second D-flip-flops, while the outputs of the shift register are connected to the inputs of the digital-analog converter, and the output of the first modulo-two adder is connected to I / O jy delay lines.