SU1751758A1 - Priority encoder - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the scope of application due to the possibility of generating the output code of an arbitrary encoding. The device introduces a group of elements UNCHARTERNESS, a switch and a group of elements NOT. The device allows for arbitrary encoding of the output code and arbitrary increasing of the output code, as well as reducing hardware costs by reducing the area occupied by the interconnect routes. 1 з п. Ф-л, 2 silt

Description

The invention relates to computing and can be used in floating point arithmetic, control devices.

A device for encrypting an extreme unit in an n-bit binary code is known, which contains the first group of partial encryption nodes, the input group of the first group of partial encryption nodes is the device input group, the switching node and the second group of partial encryption nodes, the first, second and third outputs all nodes of the partial encryption of the first group are connected to the corresponding input groups of the switching node, and their additional outputs are connected to the corresponding inputs of the partial encryption nodes of the second group, the output group The second group of nodes of partial encryption is connected to the group of control inputs of the switching node and. with the device output group, the switching node output group is connected to the device output group.

The disadvantage of this device is the inability to form an output code with a size that does not depend on the size of the input code, and an arbitrary coding. In addition, the specified device does not allow arbitrarily increasing the input code width

The closest to the proposed technical entity is an interrupt device containing two registers, a group of elements OR, a group of elements NOT and three elements AND, the inputs of the second register being the outputs of the device, the direct outputs of the 1st and the following bits of the first register ( , n - the number of requests) are connected to the inputs of the i-ro and the following elements of the OR group, the device also contains two groups of AND-NOT elements and an AND-NO element, and the outputs of the odd elements of the OR group are connected to the first inputs of the AND-NOT elements of the first group, out s J-x (. 6, 10) even elements or groups of elements through NOT group are connected to second inputs of the element (A

WITH

x |

cl

„VJ

SL 00

AND-NOT copies of the first group, the Kx outputs (, 8, 12 ...) of even elements OR of the group are connected to the first inputs of the AND-NOT elements of the second group, the outputs of the even terminals of the OR group, starting with the fourth, through the elements the groups are connected to the first inputs of the I-ME elements of the second group, the output of the first even element of the OR group is connected to the first input of the NAND element, the second input of which through the fourth element of the NOT group is connected to the output of the second black element OR group, the outputs of the NAND elements the first group is connected to the inputs of the first element And the last output output of the first register row is connected to the input of the first element AND, the outputs of the NAND elements of the second group are connected to the inputs of the second element AND, the output of the last element OR of the group is through the last element NOT of the group connected to the input of the second element AND, the first and second inputs The third element And, connected respectively with the output of the element AND-NOT and with the output of the penultimate element of the NOT group, the inputs of the bits from the first to the fourth of the second register are connected respectively to the outputs from the first to the third elements And and Exit the fourth element is not a group.

The disadvantages of the known device are limited functionality due to the strict dependence of the coding and bit) and the generated output code on the input, and raw hardware costs.

The purpose of the invention is to expand the functionality of the device by generating the output code of an arbitrary size and coding, reducing hardware costs,

The goal is achieved in that the interrupt device containing a group of elements OR is additionally introduced a group of elements NOT EQUITY, a group of elements NOT and a switch, and the output of the first element OR is connected to the input U1 of the first group of control inputs KOMMyfaTopa BxoA of the 1st element is unequal to the group (1 -1 ... n-2), where n is the number of encoder inputs) is connected to the input U1 (H-1) of the group of control inputs of the switch and through the 1st element of the NOT group with the input of U2 (A1) -th group control inputs of the switch, the output of the (n-1) -th element is NOT AVNOZNACHNOST group connected to the input (n-1) -th group of NOT circuit, a first input of a first OR gate group connected to the first data input of the encoder, a logic-zero input connected to the second

the input of the first element OR of the group, the inputs (.,. n) of the element OR of the group are connected from the first to the 1st inputs of the encoder, the inputs of the K-th element UNEQUAL DIFFERENCE of the group (,. п-1) are connected to the outputs of K-ro and (Yu 1) th elements of the OR group, the switch outputs are the encoder outputs.

In addition, the switch in the encoder

contains n groups of MOS transistors and od2P buses, with the gates of n-channel transistors of the 1st group connected to the input U1 of the 1st group of control inputs of the switch, the gates of p-channel

transistors of the 1st group are connected to the input U2 of the 1st group of the control inputs of the switch, the sources of all the transistors are the information inputs of the switch, the drains of the transistors K.1-K.1od2P

(,., p, K - group number of transistors) are connected to buses S S S (log2n-1), respectively, the buses are switch outputs.

FIG. 1 depicts priority

encoder for the case (n is the width of the input code).

The priority encoder contains a group of elements OR 1.1-1.l, a group of elements REQUIRED 2.1-2. (P-1).

group of inverters 3.1-3. (p-1), switch 4, with the output of the first element OR 1.1 connected to the input U1.1 of the first group of control inputs of the switch, the output of the element UNIMAL 2.I group

(, .. 14) is connected to the input U1. (I + 1) (it 1) of the group of control inputs of the switch and through the element NOT 3.1 of the group to the input of U2. (1ST) (AND 1) of the group the control inputs of the switch, the output of the UNEQUALITY 2.15 element is connected to the input of the HE 3.15 element, the first input of the OR 1.1 element is connected to the first information input of the Xf encoder, the logical zero input of which is connected to the second input of the 1.1 element, the inputs of the OR 1.1 element are connected to the inputs of the Hf encoder -X (S), the inputs of the UNEQUALITY element 2.K (.. 15) are connected to the outputs of the elements OR 1.K and 1. (K + 1), the outputs of the switch and S S3 are the outputs of the encoder.

FIG. 2 shows the switch for the case (n is the width of the input code of the priority encoder).

The switchboard contains 16 groups of MDPtransistors and four 5f-S3 buses, the gates of n-channel transistors of the 1st group (... 15) are connected to the input U1 i of the 1st group of control inputs of the switch, the gates of p-channel transistors of the 1st the groups are connected to the input U2.i of the 1st group of the control inputs of the switch, the sources of all the transistors are information inputs of the switch, the drains of the transistors K.1-K.4 (KM ... 16) are connected to the buses Sf - S3, respectively, buses are switch outputs.

The device operates as follows (by the example of an n-bit priority encoder, fig. 1).

The input code is fed to the inputs of the OR elements, HF is the most significant bit of the input code. Suppose the input code contains the highest unit in the lth order, then O, 1.1-1 (i-1) are set to O, and 1.1-1, and n are output to the outputs. Next, the signals from outputs.Element 1. I-. 1.p arrive at the inputs of the ELEVATOR element, the group of outputs of which forms code 1 of n (1 at the output of element 2. (1-1). The signal from the output of the element UNIMAL VALUE, at the output of which 1 (2 (i-1)) It enters the control input of the switch U1.I (Fig. 2), opening the n-channel transistors of the corresponding group, the P-channel transistors are opened with a signal from the output of inverter 3. (i-1). The specified group of transistors is installed on the S0 -S3 buses the binary code of the number of zeros before the highest unit in the input code, ZF is the most significant bit of output of the code.

Compare the functionality of the known and the proposed device. In a known device, the output code is equal to the binary code of the position number of the highest unit in the input code, and the output code is uniquely associated with the input code n as logan, which limits the functionality of the known device.

Expansion of functionality in the proposed device is achieved by the fact that the output code can be arbitrarily increased by introducing Si buses, and the desired coding can be achieved by changing the type of conductivity of MOS transistors and the potentials applied to their sources: using n-channel transistors for O, P channel transmissions - for transmission 1.

Let us compare the hardware costs in the known and proposed devices, in the case of their integral implementation, we use the following approximation: the hardware costs due to buses running perpendicular to the device inputs are equal to one input of a logic element for one bit of the input code. The hardware costs introduced by two transistors in the circuit of the proposed device coincide with the complexity of a single input of a logic element. The known device with the output code K (bit 2-2

The input code has) I

i 1

the inputs of the OR elements, the inputs of the inverters, 0 inverters, 2x () - 2x () f ... + 2x (21-1)

k - 1

inputs of elements NAND, 2nd inputs

I 1

k - 1

And elements and (2 -1) tires. perpendicular151 1

cool entrances to the device. Proposed

device contains элем element inputs 1

Combo OR, 2x (p-1) of the inputs of the UNEQUAL VALUE elements, p-1 of the inputs of inverters and nxk transistors (n, k - the size of the input and output codes, respectively). When the output code K-4 is small, the hardware costs in the known device comprise 313 inputs of logic elements, in the proposed device there are 245 inputs, i.e. in the proposed device achieved a reduction in hardware costs by about 1.3 times; long 6, hardware costs are reduced by 1.8 and 2.2 times, respectively.

Claims (2)

1. A priority encoder containing groups of OR elements, characterized in that, in order to expand the scope of application due to the possibility of generating an arbitrary encoding output code, it contains a switch, a group OR elements, a group of inequality elements, a group of NOT elements, the output of the first element OR of the group is connected to the first information input of the switch, the output of the first inequality element of the group is connected to the second information input of the switch and through the first element of the NOT group to the third information input of the switch, the output of the last element NOT groups — with the fourth information input of the switch; the first input of the first element of the OR group — with the first information input of the encoder, whose logical zero input with connected to the second input of the first element OR groups, the inputs of the 1st (, n is the number of inputs of the encoder) of the element OR the groups are connected from the first to the 1st inputs of the encoder, the inputs of the k-ro element of the unequal group (n-1) are connected to the outputs of the 1st and (i + 1) -ro elements of the OR group, the outputs of the group inequality elements are connected to the inputs of the elements of the same name NOT the group, the outputs of the switch are the outputs of the encoder, the control inputs of the switch are the control inputs of the encoder. 2. The encoder according to claim 1, characterized in that the switch contains two groups of n-channel MOS transistors. a group of p-channel MOS transistors and a p-channel MDGN transistor, with the gates of the n-channel transistors of the first and second groups connected to the first second information inputs of the switch, the gate of the p-channel transistor 0 five with the third information input of the switch, the gates of the p-channel transistors of the group — with the fourth information input of the switch; the sources of the transistors are the control inputs of the switch, the drains of the last p-channel transistor of the first group, the last p-channel transistor of the group and p-channel transistor are combined and are the corresponding output of the switch, the drains of the same n-channel transistors of the first and second groups are combined with the drains of the same-name p-channel transistors of the group and are corresponding switch outputs FIG 4 WMSJ