SU1741157A1 - Device for monitoring random processes with interference - Google Patents

Abstract

This invention relates to a computer technology designed to monitor the occurrence of random processes mixed with interference. The device contains three main memory units, three adders, two division units, a sample number setting unit, a clock generator, a multiplication unit, a control unit and a control results analysis unit, and provides an increase in productivity and quality control due to the automatic setting of the number of processing cycles. information about a random process, depending on its information and statistical characteristics. 3 of p f-ly, 6 silt

Description

The invention relates to computing technology and can be used in systems for the digital processing of information about the state of an object, arriving as a set of random processes with interference.

A device for controlling random processes with interference is known.

However, this device removes invalid values in samples of limited volume, which leads to loss of information about the monitored process at time points corresponding to excluded values, and, consequently, to low reliability of the control results with a strong distortion of the monitored parameters by interference.

It is also known to control random processes with interference, comprising a first memory unit connected in series, a first summation unit if the first division unit, and a multiplication unit, a second blocking sum, a second division unit, a counter, a second and third memory unit, a third summation unit, unit for the number of sensors to be polled, clock generator, frequency divider connected by the first control output to the first control inputs of the first division unit, the second memory unit i and the counting input account ika second control output - the gate to the first inputs of the first and third memory blocks, the control output of the third - the gate with the second input 4 -N

SL

h

The first, second, and third memory blocks, the fourth control output — with the third control input of the first memory block, and the command output — with inputs for enabling the signal processing of the memory blocks from the first to the third and third summation blocks, information input and output which are connected respectively to the second information output of the first memory block and to the information input of the third memory block, the inputs of the first and second factors and the output of the multiplication unit are associated respectively with the outputs of the third memory block and the second dividing unit and with the second information input of the first memory block, the first information input of which is connected to the device input, the code output of the counter is connected to the address inputs of the first and second memory blocks, the divider input and the output of the first division block are connected respectively to the output of the number setter interrogated parameter sensors and to the information input of the second memory block, the first and second information outputs of the second memory block are connected respectively to the output of the device and to the input of the divisible second The second dividing unit, the divider input of which is connected with the output of the second summation unit, the input of which is connected to the third information output of the second memory unit.

The known device carries out a reusable accumulation of n values of the measured parameter in m samples with optimization of these values, taking into account their statistical and energy characteristics and carried out after each accumulation cycle to increase the signal-to-interference ratio while monitoring a random process.

A disadvantage of the known device is the use of a fixed number of cycles of accumulation of values of the monitored parameter (information processing cycles), which leads to the need to adjust this value depending on the information and statistical characteristics of the monitored process.

The purpose of the invention is to increase the productivity and quality of control by automatically setting the number of processing cycles of information about a random process depending on its information and statistical characteristics.

The goal is achieved by the fact that the device for monitoring random processes with interference, containing three blocks of RAM, three adders, two

dividing unit, unit number of samples, clock generator and multiplication unit, the input of the first factor is connected to the output of the second unit

division, the input of the second multiplier - with the output of the second RAM block, and the output - with the first information input of the first RAM block, the output of which is connected with the information input

the second adder, the output of which is connected to the input of the divisible first division block, the input of the divider which is connected to the output of the sensor of the number of samples, and the output

-with information inputs of the third adder and the third block operational

a memory, the first output of which is connected to the input of a divisible second division unit, the input of a divider which is connected to the output of the third adder, an information input

the second memory unit is connected to the output of the first adder; a control unit and a control results analysis unit are entered, the output of which is connected to the stop input

control block and information input

- with the output of the second dividing unit, the input of setting the multiplication sign of the multiplication unit is associated with the significant output of the first random access memory unit, the second information input of which and the information input of the first adder are connected to the information input of the device, the output of the clock generator is connected to the clock input of the control unit, second

the output of the third memory block serves as an information output of the device, the address outputs of the control unit are connected to the address inputs of all memory blocks, and the control

outputs - with control inputs of all RAM blocks, adders, division blocks, multiplication unit and control results analysis block; control block trigger input is a trigger input

devices.

The operation of the device is based on the fact that, using the additional units introduced, the magnitude of the decrease in the sample entropy of the averaged values (current control results) obtained in this information processing cycle is compared with the entropy of the similar sample in the previous cycle:

 Hk is Hk-1, where Hk is the entropy value for the K-th processing cycle.

The information processing cycles are repeated until the AH value reaches the preset entropy value e, i.e. when the processing is completed.

FIG. 1 shows a block diagram of the device; in fig. 2 - block diagram of the analysis of control results; in fig. 3 is a block diagram of the control unit; in fig. 4-6 - diagrams of synchronization of the operation of the device blocks.

A device for monitoring random processes with interference contains an input bus 1 of the device connected to the information inputs of the first RAM 2 and the adder 3, the output of which by the first bus 4 is connected to the information input of the second RAM 5, the information output of the first RAM 2 the memory of the second bus 6 is connected with the input of the second adder 7 connected by its output via the third bus 8 to the input of the divisible first division block 9, the input of which is connected to the fourth bus 10 with the output of the setpoint 1 1 the number of samples, and the output by the bus 12 with information inputs of the third RAM 13 and the third adder 14, the first information output of the third RAM 13 is connected to the output bus 15 of the device, and the second information output through the sixth bus 16 is connected to the input of the divisible second dividing unit 17, the input of the divider which is connected to the seventh bus 18 to the output of the third adder 14, and the output to the eighth bus 19 is connected to the information input of the control results analyzer 20 and the input of the first multiplier 21 multiply, the input of the second multiplier of which is by the ninth bus 22 is connected to the output of the second RAM block 5, the input for setting the sign of the product of the block 21 is connected with the sign output of the first RAM block 2, and the output through the tenth bus 23 is connected to another the information input of the block 2, the stop input and the clock input of the control block 24 are connected respectively to the outputs of the monitoring result analysis block 20 and the clock generator 25, the control outputs of the block 24 are connected by bus 26 to the control inputs of blocks 2, 3, 5, 7, 9, 13, 14, 17, 20 and 21, the output of the sampling address of control block 24 is connected to bus 27 with the corresponding address inputs of the first 2 and second 5 blocks of RAM, and the output of the reference address with bus 28 with the corresponding address inputs of the first 2 and third 13 blocks of RAM.

The device has two modes of operation: Information I / O and Information processing.

In the mode I / O information

The device works as follows. The input bus 1 is supplied with measured at certain time intervals and digitized samples Xj (tj) of each of the m samples of the monitored parameter values (Xj (ti) - the parameter value at the i-th time for the j-th sample), which are recorded in the first block 2 RAM, and also arrive at the information input of the first adder 3, where for

every j-th sample is accumulated

Sj S Xj (ti), j 1,2m.

i 1

The obtained m results Sj from the output of the adder 3 are fed via bus 4 to the information input of the second RAM 5, where these values are recorded.

In the described mode, the control results obtained in the Information processing mode are also output from the first output of the third RAM memory unit 13 to the output bus 15 of the device.

The Information Processing mode consists of steps 1 and 2. In step 1, the operation of the device is as follows. The values Xj (ti) from the information output of the first memory block 1 via bus 6 are fed to the information input of the second adder 7, where the sum of the corresponding i-x values of all m samples is calculated

Si Z

j - 1

Xj (ti), i 1.2n.

From the output of the adder 7, the results of the summation of Si on the bus 9 are fed to the input of the divisible first dividing block 9, to the input of which the divider on the bus 10 from the output of the setter 11 of the number of samples receives the value of m.

55

(ti) | f. 1 1.2p.

The obtained average values (ti} from the output of block 9 through bus 12 are fed to the information inputs of the third block 13

RAM (here they are recorded) and the third adder 14, where these values accumulate:

EG,

 at i 1

X (t0

Stage 2 of the Information Processing mode is as follows. The values (ti) and Sj calculated in step 1, respectively, from the second output of block 13 via bus 16 and from the output of adder 14 through bus 18 arrive at the inputs of the dividend and divider of the second division block 17. In this block, -, - are defined

p (ti) 2

i iQ, I I, Ј, ..., II.

ЬЕ

From the output of block 17, the values of PJ are fed via bus 19 to the information input of block 20 analyzing the results of control and the input of the first multiplier of multiplication unit 21, to the input of the second multiplier of which the bus 22 receives the values of Sj from the output of the second RAM block 5. In block 21, the initial samples Xj (ti) are modified in accordance with the expression

Xj (t,) Pi -Sj (ti),, 2m; i

 1.2n.

The information about the sign (ti), (i.e., the most significant bit value Xj (ti) presented in the additional code) is transmitted to the input of the job sign of block 21 from the sign output of block 2.

The modified values Xj (ti) from the output of multiplication unit 21 via bus 23 go to the second information input of the first memory unit 2 and replace the corresponding initial values Xj (ti) located in this unit.

Steps 1 and 2 constitute one cycle of information processing, the total number of such cycles is determined in block 20 of the analysis of control results in accordance with the information and statistical characteristics of the result of processing - the values (tj) obtained in each cycle.

The control results analysis unit 20 (FIG. 2) contains a computational node 29. The input of which is connected to the information input of the block, and the output via the bus 30 is connected to the information input of the adder 31, the output of which is connected to the bus 32 with the input of the subtracted subtracting node 33 and information input node 34 of the RAM associated with its output via the bus 35 with the entrance of the system, -

0

five

subtracting node 33, the output of which by bus 36 is connected to the second information input of comparison node 37, whose first information input is connected via bus 38 to output of setpoint 39 of entropy increment limit, output of comparison node 37 is block output, control inputs of bus block 26 connected to the resolution inputs of the adder 31, subtracting node 33, and comparison node 37 with the write and read control inputs of the RAM memory unit 34, the computational node 29 is designed as a fixed memory node.

Unit 20 analysis of the results of the control works as follows. The values of Pi from the output of the second dividing unit 17 over the bus 19 are fed to the input of the computational node 29 (the address input of the fixed memory node). Any possible value in PI at this node is associated with the result of the expression -Pi (092 PI, which from the output of node 29 via bus 30 is fed to the input of adder 31, where the entropy calculation for the K-th information processing cycle is performed

thirty

Hk Ј P,

i 1

Ioq2 pi

five

0

five

0

five

The obtained entropy value X of the output of the adder 31 is fed via bus 32 to the input of the subtracted node 33 of the subtraction and to the information input of the operating memory node 34 from the output of which, via bus 35 to the input of the decremented node 33 of the subtraction, the value Hk-1 obtained in the previous one (K- 1) th processing cycle of information. The difference DN DN - NK-1 from the output of node 33 goes to the second information input of comparison node 37, to the first information input of which the bus 38 supplies the limit value of the entropy increment from the output of unit 39. In the case D N e, then the output The comparison node 37 generates an information processing increment signal, which is input to the stop input of the control unit 24.

The control unit 24 (Fig. 3) synchronizes the operation of the device in each of the described modes and contains a trigger 40, two dials 41 and 42 addresses of microinstructions, a switch 43, a microcommand memory node 44, a frequency divider 45 and three counters 46-48, the output of the first the counter 46 is connected to the bus 49 to the address input of the microcommand memory node 44, the output group of which is connected to the control outputs of the unit forming the bus 26, and the two outputs are connected to the load enable input of the first counter 46 and the first information input of the switch 43, the second and third infor the output inputs of which are connected to the outputs of the higher bits of the second 47 and third 48 meters, the outputs of the switch 43 are connected to the counting inputs of the second 47 and third 48 meters, the outputs of which serve as the block's output outputs, the control input of the switch 43, the forward starting input of the first setpoint 41 addresses of microinstructions and the inverse start input of the second setpoint 42 addresses of microinstructions are connected with the direct output of the trigger 40, the unit and zero inputs of which are connected respectively to the start and stop inputs of the block, the outputs of the sensor 41 and 42 addresses of microinstructions are connected by bus 50 to the installation inputs of the first counter 46, the counting input of which is connected to the output of the frequency divider 45, the input of which is connected to the clock input of the unit.

The processing of the information is triggered by applying an external control pulse to the single input of the trigger 40, which in this case allows the output of the microcommand address corresponding to the beginning of stage 1 of this mode, from the output of the first setter 41 via bus 50 to the input of the parallel load of the first counter 46, to the clock input of the counter 36 receives a sequence of pulses from the output of the frequency divider 45, which sets the required speed of information processing.

After the counter 46 with the active ratio of its load enable input is assigned the address of the first microcommand of the Information processing mode, a sequence of control signals (microcommands) corresponding to this mode of operation begins to be output to the output group of the microcommand memory 44.

The microcommand that is executed in this mode of the last, sets from the second control output of node 44 the load enable signal of counter 46, thereby providing a return to the beginning of the command sequence of one of the modes of operation of the device (thus generating a cyclical operation).

The first control output of node 44 is clocking for the second and third counters 47 and 48, the outputs of which form, respectively, the sample address bus 27 associated with blocks 2 and 5 and the reference address bus 28 associated with operative memory blocks 2 and 13 ti.

The order of issuing addresses of the sample and reference (Figs. 4-6), depending on the mode of operation of the device, is set by the switch 43 controlled by the trigger 40. In the mode

Information I / O switch 43 passes the clock sequence from the output of node 44 to the input of the third counter 48 and connects the high-order output of this counter to the input of the second counter 47. In

0 in the Processing of information mode, the clock sequence is fed to the input of the second counter 47, and the output of the most significant bit of the last one to the input of the third counter 48. When a control pulse is applied from

The 5 outputs of the control results analysis block 20 to the zero input of the trigger 40, the microcommand address on the bus 48 is set by the second setter 42, after loading this address into the counter 47, execution begins

0 sequence of microinstructions corresponding to the mode Input-output information. The operation of the device in this mode continues until the single input of the trigger 40 again receives the 5 pulse of the information processing mode.

Claims (4)

Claim 1. Device for monitoring random processes with interference, containing three 0 RAM, three adders, two dividing units, a set number sampler, a clock generator and a multiplication unit, the input of the first factor is connected to the output of the second block 5 divisions, the input of the second multiplier - with the output of the second RAM block, and the output - with the first information input of the first RAM block, the output of which is connected with the information input 0 of the second adder, the output of which is connected to the input of the dividend first division block, the input of the divider which is connected to the output of the setpoint generator, and the output to the informational inputs of the third 5 of the adder and the third RAM block, the first output of which is connected to the input of the divisible second division block, the divider input of which is connected to the output of the third adder, information input 0 of the second RAM block is connected to the output of the first adder, which is so that, in order to increase the productivity and quality of control due to the automatic setting of the quantity 5 cycles of processing information about a random process, depending on its informational and statistical characteristics, a control block and a control results analysis block are entered into the device, the output of which is connected to the stop input of the control block, and the information input is connected to the output of the second division block, the multiplier sign of the multiplier unit is associated with the sign output of the first memory block, the second information input of which and the information input of the first adder are connected to the information input of the device properties. the output of the clock pulse generator is connected to the clock input of the control unit, the second output of the third RAM block serves as information output of the device, the address outputs of the control block are connected to the address inputs of all RAM blocks, and the control outputs are connected to the control inputs of all blocks operating memory, adders, dividing units, multiplication unit and control results analysis unit; the control input start input is the device start input. 2. The device according to claim 1, wherein the control unit contains a trigger, two sets of addresses of micro-commands, a switch, a node of the memory of micro commands, a frequency divider and three counters, the output of the first counter is connected to the address input of the memory node microinstructions, the group of outputs of which is connected to the control outputs of the unit, and two outputs are connected to the load enable input of the first counter and the first information input of the switch, the second and third information inputs of which are connected to the outputs of the higher bits of the second and third a counter, the switch outputs are connected to the counting inputs of the second and third counters, the outputs of which are addressable unit outputs control the switch input, the direct start input of the first setpoint of addresses of micro-commands and the inverse start input of the second setpoint of addresses of micro-commands are connected to the direct output of the trigger, the single and zero inputs of which are connected respectively to the start and stop inputs of the block, the outputs of the setting instructions of the micro-commands are connected to the installation inputs of a counter whose counting input is connected to the output of a frequency divider, the input of which is connected to the clock input of the block. 3. The device according to claim 2, wherein the control results analysis unit comprises a main memory unit and a computational node, an adder, a subtraction unit, a comparison unit and a setter of the entropy increment limit value, the output of which is connected to the first information input of the comparison unit, the output of which is the output of the block, and the second information input is connected with the output of the subtraction node, the input of which is decremented is connected to the output of the RAM node, whose information input and input of the subtracted subtracting node The outputs of the adder, the information input of which is connected to the output of the computational node, whose input is connected to the information input of the block, the control inputs of the block, are connected to the resolution inputs of the adder, subtraction node and comparison node, and the write control and readout control inputs. 4. The device, but clause 3, of which the computational node is designed as a fixed memory node. FIG. one FIG. 2 fig.Z Mode, input-output information. issuing addresses dbort {ds} on blocks 2 and 5 of Avres1-st sample U / 1dress j-u ($ idbp / u) & fdpec m-u dt, / Sopfru bydacha address of the attribute {Ac on 5 blocks 2 s / / J ). Record the initial values of C / b) 6 block 2 bydacho on the adder 3 if Record the result / cb of the summation I Xj (Tt) 8 block5 and zero the battery in the adder J Ht-m -itIIfigA . Mode „information processing Issuance of the reference address Ac] nor 5 blocks 2 and 13 X Address of the 1st readout of the CG Address 2-dd count / t7a X Address l-g $ otsce / psg X issuing Call Log Address {As} to Vloki 2 and 5 X / - ml. Stage 1 dydach from ct od XJ (TI) from block 2 to the sum / op 7 IU „Lm tshCh - M1 ji The output of the results of the summation, / at fa) from the adder 705loch Record the results of the division (6 block 13, Lachoichmasummator%; Reset battery Ј adder 7 -ffКЯ: fftf Я (fChamper battery S adder 14, fo / tfai / ff notation / and m # tf tf / t-f S node 33 from adder Jf and t / j / ia J4 respectively F d / daughter of the result of comparing the ultrasound unit 37 per oh 24; Zeroing battery 6 adder J / but -Uif {} - ffFig .5 {keih jiL. M-tf We lie "o5ra5tot information continued) Stage 2 The output of the summation result. S and the values of M {X {Ti} by 5lots f7 from the adder M and the block fJ G. , (LIIMpcha In block 21 of the results of summation Sj, values Pi and (Ti) from blocks 5, Pi 2, respectively tk m t. m4tj Record the results of the product Xj (T modicitized / x values) in 5ok 2 from block 21 Г Г П П А А /; L Issuing PI 8 values node 9 of block 17 T „„ L «Jl 4tproduction of values of 1DO {from node 9 to adder 31 yp „„ lff-l. 6