SU1737676A1 - Device for controlling voltage inverter with output transformer - Google Patents

Abstract

The invention relates to electrical engineering and can be used in converter equipment. The aim of the invention is to simplify the device and expand its functionality. The device contains a controlled frequency divider, three RS-flip-flops 8, 10, 11, a decoder 9, a generator 5, a counter 6. The device allows you to provide the required accuracy and discreteness of controlling the output voltage of the inverter, a full cycle of resetting the output transformer and making digital voltage inverter control 2 Il.

Description

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The invention relates to electrical engineering and can be used in converter equipment.

A device for controlling a voltage inverter with an output transformer, the secondary winding of which is connected via a rectifier to a load, contains a generator, an output connected via an element NOT to the first input of the first element I, connected in series to a ring counter and a single-oscillator whose output is connected. with the integrator reset input, two zero-organs, outputs connected to the inputs of the OR element, whose output is sub-keys to the second input of the first element AND, a counting trigger connected by the input c to the stroke of the first element And the first inputs of the second and third elements And, and the outputs with the second inputs of the second and third elements And the outputs of which are intended to be connected to the control inputs of the inverter, the setting block, the output connected to the second input of the first and second zero-organs , the first inputs of which are connected to the integrator output, an offset unit, the output of which is connected to the third input of the second null organ, in addition, the ring counter input is connected to the generator output.

The drawbacks of the device are the complexity and low functionality for providing control.

The purpose of the invention is to simplify the device and expand the functionality.

This goal is achieved in that a device for controlling a voltage inverter with an output transformer, the secondary winding of which is connected via a rectifier to a load containing a series-connected generator and counter, additionally introduces a controllable frequency divider, three RS flip-flops and a decoder, The first and second outputs of which are connected respectively to the S-input and R-input of the second RS-flip-flop, and the third and fourth outputs of the decoder are connected to the S-input and R-input of the third RS-flip-flop, outputs of the second and third RS-flip The rails are designed to be connected to the control inputs of the inverter, the output of the first RS trigger is connected to the installation input in O of the counter, the outputs of which are connected to the inputs of the decoder, the output of the generator is connected to the inputs of the counter and the controlled frequency divider whose output is connected to the S input of the first RS flip-flop connected by R-input to the fourth output of the decoder.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing diagrams for the operation of the device.

A device for controlling a voltage inverter with an output transformer (Fig. 1) contains a rectifier 1, the input is connected to a transformer 2, the primary winding connected to a voltage inverter 3. The latter is connected to source 4 (for example, a battery) by poles. Serially connected generator 5 and counter 6, controlled frequency divider 7, RS-flip-flops 8, 10, 11 and decoder 9, the first and second outputs of which are connected respectively to the S-input and R-input of the RS-flip-flop 10. Third and fourth outputs decoder 9 is connected to the S-input and R-input of the RS-flip-flop 11. The outputs of the RS-flip-flops 10 and 11 are designed to be connected to the control inputs of the inverter 3. The RS-flip-flop 8 output is connected to the installation input of the O counter 6, the outputs of which are connected to the inputs of the decoder 9. The output of the generator 5 is connected to the inputs of the counter 6 and control l emogo frequency divider 7, whose output is connected to the S-input of RS-flip-flop 8 is connected to R-input of the fourth output of the decoder 9.

Counter 6, the decoder 9 and the triggers 8, 10, 11 form a pulse distributor. The controlled frequency divider 7 is conveniently performed as a series-connected divider 12 with a variable division factor and an unmanaged divider 13.

The device converts the unregulated DC voltage of source 4 into a permanently adjustable output.

The generator 5 produces square-shaped pulses (Fig. 2a), the frequency of which is: f3r Kfp, where K is the division ratio of counter 6; fp is the operating frequency of the inverter 3. These pulses go to the counting inputs of the counter 6 and the controlled frequency divider 7, the division factor of which is set by the control signal 14, represented in the form of a parallel binary code. Pulses (Fig. 26) from the output of the controlled frequency divider 7 are fed to the S-input of the trigger 8.

In the initial state, the triggers 8, 10, 11 are in the zero state, and at their direct outputs there are signals O. This causes the counter 6 to be kept in the zero state on the setup R-input, and the control signals on the input Inverter 3 are missing.

With the arrival of the pulse (Fig. 26), the trigger 8 is set to state 1, and therefore, the counter 6 removes the prohibition on counting the pulses (Fig. 2a) from the generator 5. The state of the counter 6 is controlled by the decoder 9, at the output which signals (Fig. 2d, d, e, g) are generated, controlling the triggers 10 and 11.

With the counting equal to one, on the first output of the decoder 9 (Fig. 1), a signal 1 is received (Fig. 2d), which sets the trigger 10 to the state 1.

When the counting is equal to three, the second output of the decoder 9 (Fig. 1) sends a signal 1 (Fig. 2e), which will set the trigger

10B state O.

With a count of four, on the third output of the decoder 9 (FIG. 1), a signal 1 (FIG. 2e) is set up, which will set the trigger

11 state 1.

When the count becomes equal to six, the fourth output of the decoder 9 (Fig. 1) sends a signal 1 (Fig. 2g), which sets the triggers 8 and 11 to the state O and the inverter operation cycle is completed.

As the value of the control code 14 changes (the division ratio of the controlled frequency divider 7 changes), the pulse arrival period (Fig. 26) from the output of the frequency divider 7 will change, which leads to the regulation of the pause (Tn) between two cycles (Fig. 2h) operation of the inverter 3. TP T3rNi, where Tag is the period of arrival of pulses from generator 5; N, is the variable division factor of divider 12 (the maximum value of N is chosen equal to

NMBKC (imax / imine - 1) K); Umaks. UMHH IEC is the minimum and minimum effective voltage at the output of the inverter.

To ensure the operation of the transformer 2 for the full cycle, you should choose the division ratio of the unmanaged divider 13 equal to or a multiple of K

The signals generated in this way in the form of 1 from the direct outputs of the RS-flip-flops 10 and 11 are fed to the inverter 3, which is made according to the push-pull scheme, and alternating pulses will be formed at the output of the transformer 2 (Fig. 2h).

Thus, the introduction of an additionally controlled frequency divider, three RS-flip-flops, a decoder and new connections into the device allows simplifying the device and expanding its functionality by providing digital control, while ensuring the required accuracy, linearity of the inverter output voltage regulation and output magnetization reversal transformer and remagnetization of the output transformer on a full cycle.

Claims (1)

Invention Formula A device for controlling a voltage inverter with an output transformer, the secondary winding of which is connected via a rectifier to a load, containing a series-connected generator and counter, characterized in that, to simplify and extend the functionality, three RS are inserted into it - a trigger and a decoder, the first and second outputs of which are connected respectively to the S-input and the R-input of the second RS flip-flop, the third and fourth outputs of the decoder are connected to the S-input and the R-input of the third RS-tr igger, the outputs of the second and third RS-flip-flops are designed to be connected to the inverter control inputs, the output of the first RS-flip-flop is connected to the installation input to the O counter, the outputs of which are connected to the decoder inputs, the generator output is connected to the counter inputs and the controlled frequency divider, the output of which is connected to the S-input of the first RS-flip-flop connected by the R-input to the fourth output of the decoder. I I I I I I I I I I I I I I I I I | i i i i i t n n n F and and n FIG. 2