SU1735883A1 - Telemetry data receiver - Google Patents

Abstract

The invention relates to the field of telecommunications and telecommunications and can be used in systems of telemetry and remote control signals. The purpose of the invention is to improve the noise immunity of the processing of telemetric information signals. The device performs digital coherent processing of incoming signals-1, which are used as binary signals, manipulated with a continuous phase, with a manipulation index of 0.5. To do this, a phase synchronization unit, a demodulator, a shift register, and a registration unit are entered into the device, the demodulator being designed as a coherent digital demodulator containing two correlation processing channels, as well as memory elements, adders, a switch, a comparison unit, a trigger and element I. 1 z.p. f-ly, 1 ill. % to

Description

The invention relates to radio engineering and communications, telemetry technology and can be used for digital remote control and telemetry transmission systems.

A device for receiving multi-channel information with a temporary

code division channels, which contains an amplitude discriminator, an information code processing unit, a clock synchronization unit, memory elements, a code converter and digital indicators. The time division of the channels allows a significant reduction in the bandwidth of the communication channel, however, amplitude detection has the lowest noise immunity of all known types of detection, and therefore

the reliability of information emitted by the device is reduced.

A device for receiving control and telemetry signals is known. It contains an antenna with a high-frequency amplifier connected to it, a frequency detector, a digital information converter, a clock synchronization unit, an address signal decoder, a demultiplexer, memory elements, digital-analogue converters, information recording units, executive blocks items. The use of frequency detection improves the noise immunity of processing, however, the requirements to improve the noise immunity imposed on newly developed radio systems determine the need to search for new types of signals and demodulation methods.

one

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leia, allowing to increase noise immunity of processing.

The purpose of the invention is to improve the noise immunity of processing the telemetric information signal.

The drawing shows a diagram of the proposed device.

The device for receiving telemetry information contains a high-frequency amplifier 1, a frequency detector 2, a limiting amplifier 3, a phase synchronization unit k, a clock synchronization unit 5, a demodulator 6, a station signal decoder 7, a shift register 8., a counter 9, a demultiplexer 10, a block 11 buffer registers, block 12 digital-analog converters, block 13 registration, block k contains the first and second 15 blocks of phase-locked loop (PLL), the reference generator 16, block 5 contains the block 17 of the difference. frequency, block 18 PLL, demodulator 6 contains t dispenser 19 pulses, the first 20j, the second 20g, the third 20z the fourth 204 and the fifth 5 elements And, the first 21 | and second 21 reversible counters, first 22 and second 22g memory registers, switch 23, first 2, second, third and fourth 2 4sUmmat ° Ry comparison unit 25, trigger 26, block 11 contains n buffer registers 27, ..., 27n , block 12 contains n digital-to-analog converters 28 ,, ..., 28p.

The device works as follows.

The received FMNF-FM radio signal from the output of the high-frequency amplifier 1 is fed to a frequency detector 2, the output of which the selected FMNF signal (with a manipulation index of 0.5) is converted by the amplifier-limiter 3 into a sequence of pulses that goes to the inputs of the first 1 and the second 15 PLL units, as well as to the signal input of the demodulator 6. The input of the coherent demodulator 6 are digital multipliers made on the AND elements 204 204, the second inputs of which receive the reference signals from the outputs of the AND blocks 15 and tim antiphase reference signal second inputs of AND gates 204 and 20g are inverted. The first 1 MJBTO swarm 15 PLL units, as well as the third PLL unit 18, clock synchronization unit 5 have a common reference generator

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16, with blocks 1 and 15 of the AFC being fluxed, with narrow-band tracking filters, each of which selects one of the mapped frequency of the MNF signal, as a result of which the block C has a high noise immunity. In block 17 of the clock synchronization block frequency difference, the difference frequency of the manipulated frequencies is allocated, which, when the manipulation index is 0.5, is equal to the clock frequency. PLL unit 18 serves to reduce the dispersion of clock pulses, which also increases the noise immunity of processing the MNF signals

In order to organize the necessary sequence of operation of the blocks of the telemetric information receiving device, a temporary shift of the clock synchronization signals by the pulse distributor 19 is performed. Phase mismatch signals from the outputs of the And 20-204 elements are fed to the summing and subtracting inputs of the reversing

15

20

25

counters 21 l and 212, with

0

0

five

In order to organize the demodulation process at two clock intervals, the resulting correlation values of the first and second clock intervals are rewritten into memory registers 22 and 222. At the end of the second clock interval, according to the demodulation algorithm, the correlation values from the outputs of registers 22 ,, and 22 memories

5 through the switch 23 is fed to the adders codes. The decision on the symbol at the first clock interval is made by the maximum posterior probability criterion by the comparison unit 25, the codes, which, together with the trigger 26, form the envelope of the PNC signal, i.e. transmitted address and information code sequences. The organization of such a coherent demodulation procedure allows, on average, a 1.5 dB increase in noise immunity compared to traditional demodulation processes of frequency-manipulated signals on a single clock interval.

During demodulation, there may be cases when the compared codes are equal to each other. In this case, by connecting the fifth element

5 and 20U The envelope shaping is organized in such a way that at the output of the demodulator the symbol does not change and corresponds to the symbol of the previous clock interval. After the station decoder 7 selects the station 9, an input signal is received at the input of the counter 9, which in the counter 9 generates a sequence of information address codes. According to these address codes, the information codes from the output of the shift register 8 through the demultiplexer 10 are rewritten into the block 11 of the buffer registers, each of the buffer registers 27, ..., 27 g being assigned to the corresponding information channel from the sensor on the transmitting side. the form is produced by a block 12 of digital-to-analog converters, with the output of each of the digital-to-analog converters, 28P recording analog information and a multichannel recording unit 13.

Thus, coherent demodulation of the FMN L-signals with an index of 0.5 at two clock intervals allows an increase in the noise immunity of information processing by an average of 1.5 dB compared with the processing of frequency-manipulated signals at one clock interval.

Claims (2)

1. A telemetry data reception device containing a successively connected high-frequency amplifier, a frequency detector and a limiter amplifier, a clock synchronization unit, a station signal decoder, a serially connected demultiplexer, a buffer register unit and a digital-analog converter unit, a high-frequency amplifier input connected to a receiving antenna, characterized in that, in order to improve the noise immunity of the processing of telemetric information signals, a block of phase sync is introduced into it de-modulator, shift register, counter and registration unit, the output of the limiting amplifier is connected to the first input of the demodulator and the block input by phase synchronization, the first output of which is connected to the first input of the clock synchronization block, and the second output of the block phase synchronization is connected to the second input of the clock synchronization unit; the third output of the phase synchronization unit is connected to the third 0 five 0 five 0 five 0 five 0 five The inputs of the clock synchronization unit and the demodulator, the fourth input of which is connected to the output of the clock synchronization unit, the first output of the demodulator are connected to the information inputs of the station signal decoder and the shift register, the clock inputs of the counter, shift register and the signal decoder of the station are connected to the second output of the demodule. The output of the station’s signal decoder is connected to the installation input of the counter, the information outputs of the shift register are connected to the corresponding information inputs of the demultiplexer, the address inputs of which are connected to the corresponding outputs of the counter, the outputs of the D / A converter unit are connected to the corresponding inputs of the registration unit whose output is the device output , the phase synchronization unit is made in the form of the first and second phase-locked loops and a reference generator The output of which is connected to the first inputs of the phase locked frequency units, the second single inputs of which are the input of the phase synchronization unit, the outputs of the first phase locked frequency control unit, the reference oscillator and the second phase locked frequency control unit are the first phase synchronization unit . 2. The device according to claim 1 | characterized in that the demodulator is made in the form of the first, second, third, fourth and fifth elements of AND, the first and second reversible counters, the pulse distributor, the first, second, third and fourth adders, the comparison register of memory registers, the switch and the trigger, the output of which is the first output of the demodulator, the first inputs of the first, second, third and fourth And elements are the first input of the demodulator, the second input of the first And element, and the second inverse input of the second And element and are the second input of the demodulator, the second input of the third AND gate and a second inverted input of the fourth AND gate are combined and the third input of the demodulator, the combined distributor inputs and switch pulses are fourth input of the demodulator, a first output distribution. the pulse generator is connected to the first input of the fifth element I and is the second output of the demodulator, the second output of the pulse distributor is connected to the control inputs of the first and second memory registers, the third output is connected to the installation inputs of the first and second reversible counters, the outputs of the first and second I-elements are connected respectively to the inputs of summation and subtraction of the first reversible counter, outputs of the third and fourth elements I are connected respectively to the inputs of summation and subtraction of the second roar A counter counter, the outputs of the first re-. The version counter is connected to the corresponding information inputs of the first memory register, the outputs of the second reversible counter are connected to the corresponding information inputs of the second memory register, the first and second groups of outputs of the first memory register are connected respectively to the first and second information groups of the switch inputs, the first and second groups the outputs of the second memory register are connected to the third and fourth information respectively. you d. 1733883 s switchboard input groups, first and second group of exits five the first and second groups of information inputs of the first adder, whose outputs are connected to the corresponding information inputs of the first group of inputs of the second adder, a third group of outputs of the switch connected to the corresponding information inputs of the second group of inputs of the second adder, a fourth group of outputs of the switch connected to the corresponding information inputs the first group of inputs, the fourth adder, the fifth and the pole of the output group of the switch are connected respectively To the first and second information group of inputs of the third adder, the outputs of which are connected to the corresponding information inputs of the second group of inputs of the fourth adder, the outputs of the second and fourth adders are connected to the corresponding inputs of the first and second groups of inputs of the comparison unit, the first output of which is connected to input B of the trigger, C - the input of which is connected to the output of the item And, the second input of which 0 is connected to the second output of the comparison unit. five R I