SU1734195A1 - High-speed d flip-flop - Google Patents

Abstract

Use: relates to pulsed and digital devices and, in particular, to logic elements and computer triggers. The essence of the invention: D-flip-flop contains four pnpn-transistors 1, 12, b i Java pnp-p-transistor 5, 6, four resistors 3, 7, 8, current generator 11, switching n-p pn transistor 10, reference pnp pn transistor 12, two emitter followers 1, 17. 1 Il.

Description

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The invention relates to pulsed and digital devices, in particular to logic elements and computer triggers.

The purpose of the invention is to reduce power consumption, increase speed and reliability by simplifying.

The drawing shows in principle the electrical circuit of a high-speed D) -trigger,

D-flip-flop contains from first to fourth pr-p-transistors 1ts, 1e 2 and 22- The emitters of transistors 1f, 2. ,, 2g are connected respectively through the fourth resistor 3 and the fifth resistor k with the power bus and are connected to the bases of the first and the second pp -p transistors 5 and 6, the collectors of transistors 5 and 6 are connected to the power bus, and the emitters through the third and second resistors 7 and 8 are connected to the common bus and through the resistor 7 are connected to the input of the second emitter follower the transistor 9. The emitters of the transistors 5 and b is connected to the base of the switching n - p - n transistor 10, its emitter is connected via the power supply 11 via the power supply 11 and to the emitter of the reference p -p -n-transistor 12, the collector of transistor 12 is connected to the input of the emitter follower 9 and the base of transistor 1j is 2 2 , and / 2 are connected respectively to the direct and inverse synchronous inputs of the trigger. The base of the transistor 2 is connected to the first additional output 13 of the emitter follower on the transistor 9. The base of the transistor 12 of the current switch is connected to the second additional output 1 of the emitter follower on the transistor 3. The output 15 of which is used as a forward output. The collector of the transistor 10 is connected to the common bus through the first resistor 16 and to the inverse output 18 via the first emitter follower 17. The outputs 14 and 15 of the emitter follower on the transistor 9 are connected to the power bus via high impedance resistors respectively 19 and 20.

The D-flip-flop is as follows according to the state table of the PL of the synchronization and control signals.

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The last row in the status table corresponds to the storage mode. In accordance with the state table, a synchronous D-trigger after enrollment. Neither the sync signal is set to the state pn + n at the output 15. Cr - the state at the 18 D output of the repeater 17 is responsibly realized.

According to its Functional purpose, the D-flip-flop performs on output 15 the function of delaying the input control signal arriving at the input I) of transistor 1 by one, the period of the sync signals.

From the table of states describing the operation of the D-flip-flop with para-phase clock signals on the bases of transistors 12 and 2, the state at the current time is determined by the values of the control (D, V) and clock signals (C, C). Accordingly, as part of its operation with the closure of an additional feedback control signal (from the output 13 of the repeater on the transistor I to the base of the transistor 2f, the D-flip-flop remembers its state. Since the previous state, in turn, depended on the previously supplied combination of input paraphase clock signals C and C (1h and 7-2 transistors base) and control: D - to transistor 11 base and feedback signal D from output to 2j base, then the final state of the trigger at an arbitrary time determines with a sequence of signals arriving at the inputs, i.e., the order of their respective time tracking.

The increase in D-flip-flop speed relative to standard D-flip-flops, including configurations on multiple brown switches, is due to the non-threshold nature of the base element AND-OR (at output F) on emitter followers and high output load capacity. Since the emitter repeaters on p – n – n– and

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The pn -p transistors operate in a linear mode and are characterized by 100% negative voltage feedback, therefore, they transmit control and sync signals at the highest possible speed among all unsaturated bipolar elements. In addition, since the emitter repeaters transmit an input signal with a coefficient of transmission in voltage Ј c Ј 1, to regenerate the signal, the D-flip-flop must contain a series-connected amplifier — a differential cascade at transistors 10 and 12. At the same time, based on the output transistor 9 and accordingly, at the outputs, the transformed repeater and the signal amplifier formed are summed. Due to the specifics of the summation of the signals, the delay on the non-inverting output F is several times shorter than the duration of the fronts of the signals fed to the inputs of the D-flip-flop.

The delay of the non-inverting output of the D-flip-flop is equal to the delay itself of the non-threshold element Vl-OR, approximately double the delay of the emitter follower: Јy, whereЈ is the constant accumulation time of charges in 5 times at normal activation (st - ps) The maximum speed at non-inverting output not only due to the non-threshold nature of the emitter followers and the differential amplifier in the mode of signal summation. The use of a multiemitter transistor allows the transmission of a feedback signal (D) to the base of transistor 2 with maximum speed, in addition, the output of the D-flip-flop (with output 13) is derived from the feedback signal and the influence of the input capacitance of the I-flip-flop.

Choosing the values of the resistors 7 and 8 (as well as the supply voltage E), not only the correct operation of the circuit in the signal summing mode based on the output transistor 3 is achieved, but also the reference bias on the base of the transistor 12 (through the emitter follower on the transistor 9 and high-resistance resistor 20 with exit 15). Since no additional sources are required

the reference offset is minimized by n, the power required of the D flip-flop and 1 is improved by the quality of its performance in the LSI subsystem. Thus, the proposed D-flip-flop allows you to realize the maximum input system speed (t Ld) with reduced power consumption and

JQ extended functional capabilities with respect to a known logical element.

The invention provides enhanced functionality.

jj increase in speed and decrease in power consumption when building high-quality high-speed D-triggers for high-performance digital devices and computers.

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Claims (1)

Invention Formula 0 five O five High-speed D-flip-flop containing a switching n-p-n-trans5 resistor whose collector through the first resistor is connected to the common bus and through the first emitter follower with the inverse output, the emitter through the current source with the bus n power and connected to the emitter the reference p –r –l transistor, whose bell through the second resistor is connected to the common bus and through the second emitter follower with direct output, the collectors of the first and The 5 second ppn transistors are connected to the power bus, the emitters to the first output of the third resistor, the collectors of four pnp transistors are connected to the common bus, the emitters of the first and second pnp transistors respectively through the fourth and fifth resistors are connected to the power bus, characterized in that, in order to reduce power consumption, increase speed and increase reliability by simplifying, the base of the first n - p - n transistor is connected to the D input of the trigger, the emitter is connected to the base of the first pn transistor and emitter Another pnp transistor, the base of which is connected to the direct synchronous input, the base of the second np –n transistor is connected to the first additional output of the second emitter follower, the emitter is connected to the base of the second pn –p transistor and the emitter of the fourth p - p - p - tran7173M958 the base of the resistor is connected to the collector with a reference inverse synchronous input, the emitter of the first p - P - n transistor, the base of the ketov p - p - p transistor is connected to the second Pogo transistor. , H1M output of the second emitter repeater, the second output of the third resistor.