SU1728880A2 - Character generator - Google Patents

Abstract

The invention relates to the field of automation v computing equipment, in particular, is intended for use in devices displaying information on the screen of a cathode ray tube. The purpose of the invention is to increase the speed, which is achieved by introducing a second memory block 14, a pulse shaper 15, a third 16 and a fourth 17 counters, a first 18 and a second 19 adders-subtractors, into the device that forms the device. The coordinate code X, Y of the beginning of the segment of the contour of the sign is formed in memory block 1. The code of the segments of the contour of the mark is formed by the counters 16 and 17. In the summation computers 18 and 19, the code of the beginning of the segment with the segment code is added or subtracted from the code of the beginning of the segment of the segment code. 6 Il.

Description

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The invention relates to automation and computing, in particular, is intended for use in devices displaying information on the screen of a cathode ray tube (CRT) and is an improvement of the basic invention according to the author. St. No. 1259330.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the device forming the label; in fig. 2 - functional diagram of the pulse former; in fig. 3 - functional scheme of the adder-subtractor; in fig. 4 is a diagram of a memory block; in fig. 5 - contour of figure 2 is represented; in fig. 6 are tables for programming a fixed memory.

The converting device contains an input register 1, a decoder for 2 characters, a block of 3 elements of NOT, a first memory block A, a generator of 5 pulses, an Ib element, a trigger 7, a converter of 8 codes of a sequence of pulses into a binary code, an OR 9 element, the first counter 10, second counter 11, digital to analog converter (D / A converter) 1.2 (X coordinate), digital to analog converter (D / A converter) 13 (Y coordinate), second memory block 14, driver 15 pulses, third counter 16, fourth counter 17, first adder -calculator 18, second adder-you reader 19.

Positions 20 designate the information inputs of the device (character code), 21 the signal input Set. O, 22 — impulse input Beginning of the sign, 23–26 — device outputs, respectively, sweep voltage in X and Y coordinates, synchronization signals, and backlight pulses.

Shaper 15 pulses contains. the element OR 27, the binary counter 28, the decoder 29, the elements And 30 and 31.

The adder-subtractor 18 (19) contains blocks of 32 elements EXCLUSIVE OR 33 (two microcircuits 533LP5) and an adder 34 with accelerated transfer (two microcircuits 533IM6).

The first block 4 of the permanent memory contains memory cells 35 made on chips 556 PT5.

Positions 36 to 42 denote the contour points of the sign of the digit 2.

Znapolomiruyuschy device works as follows.

Impulse passing through the input 21 Const. About to the installation inputs of the first 10 and second 11 counters (binary), and through the OR 9 element - to the input of the trigger 7 (RS trigger) and the installation input of the converter 8 of the pulse sequence to the binary code, the first 10 and second 11 counters and the converter 8 are set to the zero state, RS-flip-flop 7 - to the position when the clock pulses do not pass through the information input of the converter 8 through the element And b from the generator 5 of the pulses.

Impulse Start of the sign at the entrance 22

0, the character code is written to input register 1, and RS-flip-flop 7 flips to the position in which the clock pulses of the repetition rate F arrive at the information input of the converter 8. The leading digits of the character code from the first group of outputs of the input register 1 arrive at the input of the decoder 2 signs and signs are converted into signs of a group of characters that arrive at the control inputs of the first and second 14 blocks (constant)

0 memory (at the inputs for sampling resolution Vi V2 of microcircuits 556РТ5, and the inverted signs of groups of characters are fed to the inputs of Ouse V4 of the same microcircuits).

At the first address inputs of the first 4 and

5 of the second 14 blocks of permanent memory (address inputs AO - AZ chips 556РТ5) receive the lower digits of the character code from the first group of outputs of the input register 1, and the second address inputs (address

0 inputs A4 - AA microcircuit 556РТ5) - from the outputs of the converter 8 enters the code of segments of characters.

The first block 4 of the permanent memory forms the code X and the code Y the beginning of the contour piece

5 characters (points 37 - 43 contours of the sign of the digit 2), the voltage of the illumination of the sign and the pulse of the end of the sign (synchronization).

The second fixed memory unit 14 produces pulses, from which in the pulse generator 15 signals are generated to control the operation of the third 16 and fourth 17 (binary) counters and the signals controlling the operation of the first 18 and second 19 adders-subtractors.

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The inputs of the element OR 27 and the first inputs of the elements 30 and 31 receive signals from the second block 14 of the permanent memory. The output of the element OR 27 is connected to the installation input of the binary counter 28, to the counting input of which the generator 5 receives pulses with a repetition frequency 4F. The outputs of the counter 28 are connected to the inputs of the decoder 29. the output of the decoder

5 is connected to the second inputs of the elements 30 and 31, the outputs of which are the outputs of the pulse shaper 15 arriving at the installation inputs of the third 16 and fourth 17 counters.

An example of the programming tables for the 556PT5 microcircuits of the first A and second 14 blocks of permanent memory is shown in FIG. 6

Uncountable inputs of the third 1.6 and fourth 1.7 counters are fed from the generator 5 pulses with a frequency of 4F. In the subtractor 18, the code V of the beginning of the character contour segment is summed with the segment code received from the third counter 16 if a logical zero voltage signal is applied to the control input from the second fixed memory unit 14 (Log. O) or is subtracted if the control signal has a voltage of the logical unit (Log. 1).

The information inputs of the full adder 34 with accelerated transfer receive the Y code of the beginning of the segment, and the inputs of the block 32 elements EXCLUSIVE OR 33 receive the code from the output of the third counter 16. At receipt from the second block 14 the permanent memory to the control input of the voltage Log. The code from the output of the third counter 16 through the block 32 EXCLUSIVE OR 33 elements passes to the second information outputs of the full adder 34 with accelerated transfer and is added to it, if there is a Log on the control input. 1 code from the output of the third counter 16 in the block 32 EXCLUSIVE OR elements 33 is converted into an additional code that goes to the second information inputs of the full adder 34 with accelerated transfer, in the adder the code from the output of the beginning of the segment was subtracted from the third counter 16,

The functional circuit of the adder-recipient 19 and its operation are similar to the sum- tor-subtractor 18.

In converters 12 and 13, the code from the outputs of the adders-subtractors 18 and 19 is converted into a voltage sweep of the Y, X sign. At the end of the formation of the voltage sweep of the Y, X sign at the synchronization output of the first block of 4 permanent memory, a pulse is formed. The end of the sign goes to the counting input of the counter 10 and to the output 26 of the device and through the OR element 9 to the input of the RS flip-flop and the converter 8.Im- pulse The end of the sign entering the RS-flip-flop 7 will transfer the flip-flop to the position in which the output voltage is given at its output. 0y Voltage log. О will prohibit the passage of clock pulses through the element I 6 to the input of the converter 8. The pulse The end of the sign entering the second input of the converter 8 sets it to the zero position. When a pulse arrives at the end of the sign on the counting input of the counter 10, at its output the code will change to

unit The output code of the counter 10 is fed to the inputs of the higher bits of the converter 12 of the code on the X coordinate. When the code on the input of the converter is changed by one, on its output, the voltage on the next five signs on the X coordinate will be formed. .

Impulse of the final sign, the output 25 of the device enters the control unit (on

0 drawing not shown), which generates a signal about the end of the formation of the sign. After 2 µs, the new impulse arrives at the input 22 from the control unit and the sign formation process is repeated.

5 process of repeating the formation

unfolding of signs passes until

the last character in the string is not formed.

Upon completion of the formation of the sweep by the last character in the line from the output of the counter

0 10 to the input of the counter 11 receives a pulse, as a result of which the code at the output of the counter 11 changes by one. The output code of the counter is 11, arriving at the high bits of the converter of the 13 code along the Y coordinate,

5 will form a step in the converter.

The voltage generation of the character sweeps, the voltage of the steps in the row and the voltage of the steps of the rows is repeated and repeated until the last character in the last row is formed.

EFFECT: increased speed of formation of stresses.

5 sign scans, due to the fact that the coordinate of the beginning of the segment is formed in the fixed memory block in the proposed device, and the intermediate points of the segment are formed with a frequency exceeding the beginning of the shortest segment by the permanent memory block four times. Thus, the speed of the formation of character sweeps is quadrupled.

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Claims (1)

The invention claims the device according to the author. St. No. 1259330, which means that, in order to increase the speed of the device, a second memory block, a pulse shaper, third and fourth counters, first and second subtractors, subtractors, whose outputs are connected to the inputs, are entered into it respectively first and 5 of the second digital-to-analog converters, the outputs of the second group of the input register are connected to the address inputs of the first group of the second memory block, the forward and inverse samples of which are connected respectively to the outputs of the character decoder decoder and the block of elements NOT, the address inputs of the second group of the second memory block are connected to the outputs of the code converter, and the outputs of the group to the information inputs of the pulse driver, the control input of which is connected to the second output of the pulse generator connected to the counters the inputs of the third and fourth counters, the control inputs of which are connected respectively to the first and second outputs of the pulse former, the outputs of the third counter are connected to the information the first group of the first adder-subtractor, information inputs of the second group of which are connected to the outputs of the first group of the first memory block, the outputs of the fourth counter are connected to information inputs of the first group of the second accumulator-subtractor, information inputs of the second group of which are connected to the outputs of the second group the first memory block, the control inputs of the first and second totalizer-subtractors are connected respectively to the first and second outputs of the second memory block. From the channel 27 28 "I 2 15 29 36 Not the third dboichny syche / pchik -. : J / How does the tijot / ww meter count Fiel 5