SU1711327A1 - Adc tester - Google Patents

Abstract

The invention relates to radio engineering and can be used in devices for the automatic measurement and control of nonlinearity of analog-to-digital converters (ADC). The purpose of the invention is to improve the accuracy of measuring the nonlinearity of the ADC. The proposed device contains a series-connected noise generator 1, an adder 3, a tested A / D converter 4, a drive 5, a Fourier transform unit 6, an error calculator 7, an indicator 8. The test signal uses the sum of the harmonic signal and noise. Using the fast Fourier transform block, the output signal spectrum of the ADC under test is calculated. The resulting spectrum is used in the error calculator to form nonlinearity values for the corresponding value of the output code of the ADC. 1 hp f-ly, 2 ill.

Description

I.

FIELD: radio engineering.

and can be used in devices

automatic control and measurement of the accuracy of analog-to-digital converters (ADC).

The aim of the invention is to increase the accuracy of measuring the nonlinearity of an ADC with a monotonic conversion characteristic.

Figure 1 shows the functional diagram of the device; Fig. 2 is a functional block diagram of the control unit.

The device contains a noise generator 1, a harmonic signal generator 2, an analog adder 3, a tested A / D converter 4, a drive 5, a fast Fourier transform unit 6, a calculator 7, an indicator 8, a control unit 9.

The transmitter 7 is made on the divider 10, the random access memory (RAM) 11, the multiplier 12, the adder 13,

block 14 delay, subtractor 15, comparators. 16 and 17, element 18, block 19 keys, block 20 delay, adder 21, divider 22, subtractors 23-25, divider 26, multiplier 27, counters 28-30, adders 31 and 32, permanent storage device (ROM) 33.

The control unit 9 is executed on the generator 34 clock pulses, the counters 35 and 36, the one-shot 37, the ROM 38, the toggle switch 39.

The device works as follows.

After connecting the tested ADC to the device, the initial installation of the harmonic signal generator 2 by the signal from the control unit 9 occurs. The test signal is generated by adding in the analog adder 3 the output signals of the generator 1 noise and the generator 2 of the harmonic signal. The sum signal is a harmonic signal S (t) cos a) tc with a maximum signal for testing W

: X |

ADC amplitude, taken per unit, with the addition of the swinging noise with an amplitude equal to half the quantization interval (half the least significant bit of the ADC 4).

After the analog-digital conversion of the total test signal, the output signal of the A / D converter 4 is fed to the input of accumulator 5. The accumulation time in accumulator 5 is set by a signal from block 9. Synchronous with generator 2, the accumulator 5 is provided with a signal (output V) from control block 9. When averaging the output signal of the A / D converter 4 in accumulator 5, the quantization noise is attenuated, and the nonlinearity noise remains unchanged.

The signal from the output of accumulator 5 is fed to the input of block 6, in which the digital test scores of the test signal are converted into a spectral region. The processing time of the Tobr-in-6 block is determined by the signal from control block 9. The spectrum of the signal at the output of block 6 contains, in addition to the main component of the test harmonic signal of its harmonic, carrying information from the nonlinearity ADC 4.

The digital spectrum of the signal is fed to the error calculator 7. In this case, the second input of the calculator 7 receives the clock pulses, and, on the third input, the control signal from the control block 9. From the output of the calculator 7, the errors to the input of the indicator 8 are the values of the integral 6 (and the differential 6th nonlinearity, as well as the weight value W; i -th quantization level of the tested ADC (output ADC code), for which the nonlinearity value was calculated.

To describe the algorithm of the calculator 7 error, it is sufficient to represent the real ADC as a serial connection of a non-inertial nonlinear element (BNE) and an ideal ADC (ADC with zero error).

When a harmonic signal passes through the BNE, harmonic components arise that are uniquely associated with the BNE conversion characteristic. The signal from the output of the BNE is fed to an ideal ADC (ADC without error), which introduces quantization noise. Analytical characteristics of the BNE transform F (S) with a harmonic input signal with an output signal spectrum can be written as

F (S) -N2enTn (S) ((1)

by

where S is the input signal of the ADC (S cos u) t);

an - spectral samples of the output signal (harmonics of the input signal);

Tn (S) is a Chebyshev polynomial of order n; N is the number of quantization levels.

Knowing the output value of the ADC code for the 1st quantization interval, it is possible by sequential enumeration of Si values from

interval Wi ± (бL +) + - with a step (5 (Wi is the weight of the i-th quantization interval; d i is the maximum integral nonlinearity of the ADC; D is the smallest

significant bit of ADC; 3 W is the maximal differential nonlinearity of the ADC) and the comparison calculated by the formula (2)

20

+ 2

where No is the number of samples for one period of the harmonic signal;

m is the ADC resolution, f (Si) s

the known value of f (St) for the boundaries of the 1st quantization interval of an ideal ADC determine the real values of the boundaries of the quantization intervals, and knowing them, the magnitude of the integral and differential nonlinearities of the 1st quantization interval of the tested ADC.

The spectral components of the averaged signal from the output of block 6 are recorded in RAM 11. At the same time, the address input

The RAM from counter 28 receives the codes of the addresses of the spectral components in the RAM. From the output of the control block 9 to the input of the counter 28 receives clock pulses. On the control input of the RAM 11 of the block 9 controls

Signal Record comes.

After recording the N + spectral components (N 2nvK), the error calculator 7 is outputted by the signal from the output of control unit 9 to the nonlinearity calculation mode. The formation of Si values is carried out as follows.

At the output of counter 29, a sequence of codes is formed corresponding to the numbers in the interval (-K / 2, K / 2), where K is the division ratio of counter 29. The signal from the output of counter 29 goes to the normalizing multiplier 27, which multiplies the input numbers by 2

the mask: Ј (5i; + d w / 2). At the exit

normalizing multiplier 27 receive a sequence of numbers (5) from the interval {- (d w / 2 4- dt), (d w / 2 + d)} with step

(2c5) / K. The number K is chosen from the condition (2c5 | + b LD) / K it, where it is the required measurement error of the nonlinearity of the ADC under test. From the output of the multiplier 27, the sequence of numbers goes to one input of the adder 32, to the other input of which the code of the measured ADC quantization level is applied, formed in the counter 30 and folded in the adder 31 with the value (1/2) L (D is the ADC quantization interval width) . The value (1/2) D is continuously fed to the second input of the adder 31. The codes at the ADC output are in the range of 11 ... 12. The division factor from counter 30 is equal to the number of output levels of the ADC under test.

Thus, at the output of the adder 32, a value is formed in the form of Si Wi + (5 {+ 1 / 2Д. (3)

Next, in the error calculator 7, the value f (Si), which is determined by the formula (1), is generated for comparison with the output code of the ADC. In this case, the values of Tn (Si) are read out from the ROM 33.

 . (

.Nip N, 0}. .. -.

, 2Т0 (5;) - (12NO

. T ° (51 U2-L4,.-Q,

where TN (SI) is the Chebyshev polynomial, NI 0,1.

Such normalization of polynomials is equivalent to bringing the output signal of the A / D converter 4 into the range-1 ... 1.

Nc 2m + 1 numbers of spectral components with a resolution of t + 1 from counter 28, which has a counting factor of 2m + 1, i.e. A code is supplied to the address input of ROM 33

AHFD - 2m + 1- SH-Ni,

N

where NI is the spectral component number from counter 28.

The values of the spectral components an are fed to the first input of the multiplier 12, and to the second input - the values of Tn (Si). In this case, the address input of the RAM 11 receives the address codes from the counter 28 (Kdel 2), and the control input receives the Read signal from the control block 9. The resulting product an Tn (Si) is fed to the first input of the adder 13, to the second input of which comes from the delay block 14 a previously calculated sum at the first summation for each value of Si, from block 14 on

S

the adder 13 enters zero, to reset to the second input of the delay unit 14, the transfer signal is received when. going to the zero state of the counter 28. Then in the subtractor 15 from the sum

 an Tn (Si) subtracts the value of W | f

0

+ -p D, which is fed to the second input

 -., rt

subtracting the output of the adder 31. The obtained value simultaneously arrives at the first and second comparators 17 and 16, where it is compared with the values of o and -o, respectively. In this case, if the input code of the comparator 17 is less than the value of op, the logical G is formed at its output. If the input code of the comparator 16 exceeds the value of - o, then logical 1 is formed at its output.

The signal from the outputs of the comparators through the element And is fed to the second input of the delay block 20 and to the control input of the block

19 keys, the information input of which is the value of Si Wi +, 1/2 D −f 3 |.

The signal at the output of block 19 is the value of the input signal of the ADC, which corresponds to the upper limit of the measured 1st quantization interval. The output signal of the block 19 is fed to the block

20 delay, the delay time of which is equal to the time required to calculate the next value of Si. At the output of the adder 21 receive a value equal to SH-I + Si,

and the output of the subtractor 24 is an amount equal to Si + i - S /. Then, using divider 22 by two, subtractor 23, the Wi code is fed to the second input, and the second divider 26 is given the value of integral

nonlinearity ds, it is fed to indicator 8, while

3t,

Si + S + 1

-Wi, (4)

45

Subtracting the value of the subtractor 24 from the output signal (BV to the subtractor 25 and applying the difference signal to the third divider 10 by two, we obtain the value of the relative differential nonlinearity of the 1st ADC quantization interval in accordance with the expression

55

o LD /} S +1 - Si - D. (five)

The value b of A is fed to indicator 8.

Simultaneously, from the output of the counter 30 (Kdel 2t), indicator 8 receives the value of Wi - the weight of the 1st level of quantization of the ADC under test. Further, the cycle is repeated for all subsequent codes of counter 30 corresponding to the output codes of the tested A / D converter.

The operation of the proposed device is based on the equivalence of the representations of the measured ADC in the form of a serial connection of the BNE and the ADC without errors. The characteristic of BNE with harmonic input signal with frequency

fc-2- m a) .fg. (6)

where fg is the sampling rate from the test

signal

can be determined by signal spectrum

at the output of the ADC (formula 1).

To measure the non-linearity, the true values of the quantization interval boundaries are calculated from

F (St) -S anTn (s) Si, (7)

where Sf is the value of the 1st limit of the quantization interval in the ADC without errors;

Si is the actual value of the boundary of the 1st quantization interval.

The accuracy of measuring the nonlinearity of the ADC in the prototype device is determined by the expression

,(eight)

where a is the mean square measurement error;

di is the integral nonlinearity of the reference ADC ,. ..

In the proposed device, the measurement accuracy is determined by the accuracy of the BNE approximation in the equivalent circuit of the measured ADC. The accuracy of the approximation is equal to the sum of the unaccounted harmonic components. When the device operates, such non-sensible components include the harmonics of the sinusoidal signal input to the measured ADC. The rms error of the device in question

b

(9)

d6

JttfVn

2

(10V

Since H

k

h

(eleven)

where Kg is the nonlinear distortion factor of the sinusoidal signal; Sn is the amplitude of the nth harmonic of the harmonic oscillation,

and the amplitude of the signal at the ADC input is taken as one, then

15

(12)

The harmonic ratio of generator 2 can be found as

Kg -

one

T

,(13):

where KF - the attenuation coefficient of the filter;

PC power of a sinusoidal signal of a single amplitude (Pc 1/2);

Рш is the power of quantization noise and nonlinearity noise at the DAC output.

3 -2

2t

+ 4d1, (14)

where t is the number of binary bits of the D / A;

5 | - integral non-linearity of the DAC.

Taking into account expressions (14), (13) (12) receive

but

1 kf

g- /

five

0

five

The control unit 9 operates as follows.

After connecting the measured ADC to the device, a one-time closure of the toggle switch 39 is performed, from the output of which logical 1 goes to the inputs of the installation of the first and second counters 35 and 36 and to the output of the block. The signal from the first output of the counter 36, as an address, is fed to the address input of the ROM 38, the cell corresponding to this address contains the division factor necessary to obtain the required accumulation interval. After K + 1 is input to the input of the counter 35 (K is the division ratio from the ROM), the pulse of counter 36 increases its contents by one and the logical output 0 appears at the first output of counter 36, and logical 1 appears at the second output.

The signal from the second output of the counter 36 is fed to the address input of the ROM 38 to read the new division factor of the counter. 35. The control unit produces at the outputs three intervals of different duration. After forming the third interval, the signal from the fourth output of counter 36 prohibits the operation of the first counter 35 and the operation of control block 9 is resumed after switching the toggle switch 39. The signal from the output of block 9 is used for ycfaHOBKH of the harmonic generator 2, the signal from the one-shot output is used to reset the accumulator 5 .

Claims (2)

The formula was invented and 1. An analog-to-digital converter control device containing a harmonic-signal generator / serially connected drive and a fast Fourier transform unit, a control unit, the first output of which is connected to the installation input of the harmonic signal generator, the second output - to the control input of the unit fast Fourier transform, and the third output - with the first control input of the accumulator, the display unit, characterized in that, in order to expand the scope of application due to the possibility of measuring and non-linearity of the converter, a noise generator, an analog adder and a calculator performed on a random access memory, two multipliers, four adders, two delay blocks, four subtractors, two comparators, three counters, a constant memory, three dividers, a key block and an element, the first and second inputs of which are connected respectively to the outputs of the first and second comparators, and the output - to the control inputs of the key block and the first delay block, information inputs which are combined with the corresponding first information inputs of the first adder and the first subtractor and connected to the corresponding outputs of the key block. And the outputs - to the corresponding second information inputs of the first adder and the first subtractor, whose outputs through the second subtractor and the first divider are connected to the corresponding first information inputs of the display unit, the second information inputs of which through the second divider are connected to the corresponding outputs of the third subtractor, the first information whose inputs through the third divider are connected to the corresponding outputs of the first adder, and the second information inputs are combined with the corresponding third information inputs of the display unit and the corresponding first information inputs of the second adder and connected to the corresponding outputs of the first counter, the estimated input of which is connected to the output of the higher resolution Yes, the second counter, the outputs of which are connected to the corresponding first information inputs of the first multiplier, and the counting input - with The high-pass bit of the third counter, the outputs of which are connected to the corresponding address inputs of the random access memory and the permanent memory, the transfer output is connected to the control input of the second delay unit, and the counting input - with the fourth output of the control unit, the fifth and sixth outputs are connected respectively to the second control input of the accumulator and the input Write-read random access memory, the information inputs of which are connected to the corresponding output dami of the fast Fourier transform unit, and the outputs with the first information inputs of the second multiplier, the second information inputs of which are connected to the corresponding outputs of the fixed memory, and the outputs with the corresponding first information inputs of the third adder, the second information inputs of which are connected to the corresponding outputs of the second block delays, and the outputs with the corresponding information inputs of the second delay block and the first information inputs of the fourth deduct Ate, the second information inputs of which are combined with the corresponding first information inputs of the fourth adder and connected to the corresponding outputs of the second adder, and the outputs are connected to the corresponding first information inputs of the first and second comparators, the second information inputs of which, as well as the second information inputs of the second subtractor, the first multiplier and the second adder are the corresponding buses of the given codes, the outputs of the first multiplier are connected to the corresponding second and Information inputs of the fourth adder, the output of which is connected to the corresponding information inputs of a permanent storage device and a key block, the output of the generator the harmonic signal is connected to the first input of the analog adder, the second input of which is connected to the noise generator, and the output is the output bus of the device, the input bus of which is the information inputs of the drive. 2. A pop device, 1, characterized in that the control unit is made on a clock pulse generator, a one-oscillator, a persistent storage device, two counters, and a toggle switch, the output of which is the first output of the block and -1 second counters, counting input first0 The first of which is connected to the output of the clock generator and is the fourth output of the block, the preset inputs are connected to the corresponding outputs of the persistent storage device, the address inputs of which are connected to the corresponding outputs of the second counter and are respectively the third, second and sixth outputs of the block, the fifth the output of which is the output of the one-shot, the input of which is connected to the output of the low-order bit of the second counter, the output of the most significant bit of which is connected to the input of the Inhibit counting of the first Meters withstand. I