SU1709311A1 - Commutator - Google Patents

Abstract

The invention relates to computing technology and allows, on its basis, to create parallel processors, multi-module computing and multitransputer systems that form parallel graphs of semantic networks. The purpose of the invention is to expand the scope by eliminating blocking conditions with parallel tuning of the plane switching structure. A switching device containing four keys, four trigger ^ E ”, two vortex registers, three AND elements, four OR elements, the first information input of the device being connected to the info | emacion inputs of the first input register, the first and second keys, the second information input - to the information inputs of the second input register, the third and fourth keys, the cfipocf input, synchronization inputs and two information outputs, additionally contains the configuration register, the first and second elements! NOT AND. the first and second elements are NOT, from the first to the fourth comparison circuit, the delay element. The introduction of these elements makes it possible to conduct in a flat switching structure on these devices a parallel mapping of the program with non-uniform connections, which excludes blocking states and the realization of all submitted applications for connections. 4 il. '' S. * - IVI o th with

Description

The invention relates to computing and is intended for the construction of parallel processors, multi-module computing systems and multi-transport systems.

The purpose of the invention is to expand the field of application by eliminating blocking conditions in parallel adjustment of a flat switching structure.

FIG. 1 shows a functional diagram of the switching device; in fig. 2

- a list of the switching device state when it implements non-blocking non-single substitutions on the flat switching structure; FIG. 3 illustrates an example of a multiprocessor computing system in which a flat switching structure for communicating processors is performed on 10 given switching devices; in fig. 4 is a timing diagram of the formation of clocked pulses from the processors in FIG. 3 on switching devices in a flat switching structure with parallel tuning to programs of non-single connections.

The switching device (Fig. 1) contains input 1 of the setup code, two information inputs. 2 and 3, two input registers 4 and 5, four keys 6–9, two information outputs 10 and 11, four triggers 12–15, four comparison circuits 16–19, two elements NOT –– 20 and 21; setting register 22, two elements NOT 23 and 24, three elements AND 25-27, four elements OR 28-31, reset input 32 and two device sync inputs 33 and 34, delay element 35, third device sync input 36.

As can be seen from FIG. 2, the switching device 1 can be configured in a planar switching structure to eight different states, which are indicated by az. Moreover, X2 and Xs denote consecutive codes on information inputs 2 and 3. And Xm is the setup code recorded in setup register 22.

The example of a multiprocessor computing system shown in FIG. 3 is made with a flat switching structure. in which are combined ten switching devices 3746 into a triangular sorting network of the U. Kauts type. and also contains processors 47-50, which are connected to switching devices in a planar switching structure 51 for organizing configuration management and data transmission.

As can be seen from FIG. 4, in one column, the ordinate indicates the number of the synchronization input 33, 34 or 36 of the switching device 37-46, and in the other column the number of the switching device to which the corresponding moment of time indicated in the diagram is applied.

Consider the operation of switching devices in a flat switching structure with. parallel to the non-blocking setting in it of arbitrary non-single substitutions between the outer poles of eie4 and ei - e4 in fig. 3. It is assumed with .that that the set of poles ei - e4 are output, and the set of poles ei 64 is considered input when transmitting switched information through a flat switching structure 51. Obviously, in N steps, where in this case, there are 47-50 processors will form on their control outputs indicated in fig. 4 pulse timing diagram. For example, we will first generate a pulse 3733 to the first sync input 33 of the switching device 37, the first processor 47, which also generates pulses to the other synchronization inputs of the switching devices 37 and 38 via the buses shown

in fig. 3. At the same time, the pulse from the last control output of the processor 47 goes to the control input of the processor 48, which will then generate pulses on

clock inputs 39-42 switching. From the last control output of the processor 48, a pulse arrives at the control input of the processor 49, which respectively generates the synchronization pulses to the switching devices 43-45, and from its last control output sends a signal to the control input of the processor 50, which then sends the synchronization pulses on connector 46 and

from its last control output will generate a signal to the second control inputs of the processors 47-50, thereby informing them about the end of the cycle of parallel tuning of all connections in the flat switching structure 51.,

It is assumed that the registers 22 through the inputs 1 of the switching devices 37-46 before starting the display of a program of non-single communications, are represented, for example, by a non-single substitution of the form

ei e2 non e4

ea e2 ei ei

the codes of the corresponding columns of the flat switching structure 51 must be entered. Thus, the processor 47 must write the code of the First column in the registers 22 5 of the switching devices 37-42, the processor

48- code of the second column in the registers 22 devices in 39. 41, 44 switching, processor

49- code of the third column in the registers 22 of the devices 43 and 45 switching. and the processor

0 50 - code of the fourth column in the register 22 of the device 46 switching. As the register 22 can be used both serial and parallel register. Therefore, the recording can be kept in it either

5 serial, or parallel code. Since this process does not reflect the essence of the operation of the devices 37-46 switching in the process of parallel tuning to the given non-single substitution, then

0 fig. 3, these links are not shown for entry 1 of the setup code.

Consider the single operation of each switching device (Fig. 1). Its information inputs 2 and 3 can be received

5, respectively, codes X2 and Xs, which, in the presence of signals at the first synchronization input 33, are recorded in the first and second input registers 4 and 5. Similarly, after the secondary input to the synchronization input 33 of the pulses, the synchronization inputs of the first and second input registers 4 and 5 will be excited and from them are considered codes X2 and Xs, which must pass to information outputs 10 and 11 and arrive in a flat switching structure at information inputs 2 and 3 of other switching devices connected in a row and column to the previous one are similar switching device. Pushing through the X2 and Hzn codes, information outputs 10 and 11 depend on their relationship with each other, i.e. X2 Xs. Ha-Xs or Ha-Xs, as well as comparing codes X2, Xs, with code Xt in register 22. Depending on these relationships, eight states can be fixed in the switching device (Figure 2), which is determined by the inclusion of the corresponding triggers 12 -15 through their installation inputs in G (denoted by S in Fig. 1). The signal is fed to the inputs of the setup into 1 flip-flops 12-15 from the elements OR 28-31, and the flip-flops 1215 are switched at the moment when the signal is generated at the third synchronization input 36 of the device, which is connected to their synchronization inputs. The high potential from the single outputs of the flip-flops 12-15 is fed to the corresponding control inputs of the keys 6-9 and opens them for pushing the codes Xa and Xs through them.

As a result of the code comparison, the signals on the four elements OR 28-31 are formed on the four comparison circuits 16-19. Moreover, the inclusion of comparison circuits occurs at the moment when a signal is sent to the second input 34 of the device synchronization, the potential from which includes the first, second and fourth comparison circuits 16, 17 and 19 directly through their right gating inputs, and the third comparison circuit 18 through delay element 35 and its first gating input.

Let us analyze all sorts of situations using codes X2, Xs and Xf and the sequence of operation of the elements NON-20-27 and the four circuits 16-19 comparisons.

In the case when, a high potential is formed at the output of the element NE-20, and, conversely, when, then a high potential appears at the output of the element NE-21. Depending on these potentials, the HE elements 23 and 24 and the AND elements 25-27 are included through the second gating inputs of the first, second and fourth circuit 16,17 and 19 of the comparison. The formation of a similar turn-on signal for the third comparison circuit 18 at its second gating input occurs when a signal appears at the output Less than the second comparison circuit 17.

Let X2 O and Xs O, and X2 Xt (cm, row a in the table in Fig. 2). Then at the output of the element is NOT-AND 20 low potential, and at the output of NOT-AND 21 high. In this case, 5 with these potentials through element NO 23 opens element And 25, which prepares the first comparison circuit 16, the operation of which begins after the signal is applied to the second synchronization input 34 of the device. Since the codes X2 and X are equal, a high potential output is formed equal to the first comparison circuit 16, which through the first element OR 28 includes the first trigger 12 into a single

5 state that provides the connection of information input 2 with information output 10 through the public key 6.

Let X2, X2 Xg and Xs O (see line b in the table in Fig. 2). Then the output is excited more than the first comparison circuit 16, the potential from which through the second element OR 29 switches on the trigger 13, which ensures the connection of information input 2 to the information output 11 via the public key 7.

Let X2 O, Xs Xg and Xs O (see the line in the table in figure 2). Then at the output of the element is NOT-AND 20 high potential, and

0 output NOT-21 low. In this case

these potentials through the element NOT 24

element opens And 27, Rotopy prepares a fourth comparison circuit 19,

operation of which begins after a signal is applied to the second synchronization input 34 of the device. Since the Xs and XL codes are equal, a high potential is formed at its output equal to that, through the third element OR 30, turns on the third trigger 14 into a single state, which ensures the connection of information input 3 to information output 10 through the public key 8.

Let Xs Xg ,, Xs O (see line

5 g in the table in FIG. 2). Then in the included

a fourth comparison pattern 19 occurs

arousal exit More potential with

which through the fourth element OR 31

 includes the fourth trigger 15, which provides the connection of information input 3 with information output 11 through the public key 9.

Let X2 0 and Xs 5 0. and X2 5 Xs (see lines e and e in the table in Fig. 2). At the exits

5 elements NOT-AND 20 and 21 there are low potentials, by which through elements NOT 23 and 24 an element AND 26 opens, preparing the second comparison circuit 17 for operation, into groups of information

The inputs are respectively given codes X2 and Xs. When a signal is applied to the second input 34 of the device synchronization, the second comparison circuit 17 is triggered, which provides a comparison of the codes X2 and Xs.

If the code is X2 Xs, then the output is excited more in the second comparison circuit, the second and third elements OR 29 and 30 trigger, and when a signal is sent to the third output 36 of the device synchronization - the trigger 13 and 14 are switched on, which provides the connection of information input 2 to the information output 11 via key 7, and information input 3 with information output 10 via key 8.

On the contrary, it triggers if the code is X2 Xs, i.e. Less output is generated in the second. Comparison circuit 17, the potential of which includes triggers 12 and 15, which connects information input 2 with information output 10 via key 6, and information input 3 with information output 11 through key 9.

If the code (see lines g and 3 in the table in Fig. 2), then the output is excited equal to the second comparison circuit 17, the potential of which includes the third comparison circuit 18 through its second gating input. After the signal to the second synchronization input 34 is sent through The delay element 35 triggers the third comparison circuit 18, on the groups of information inputs of which codes X2 and Xg are applied. If X2 Xg, then the output is equal to the third comparison circuit 18, the potential of which includes the triggers 12 and 14, and thereby provides communication between information inputs 2 and 3 and information output 10 via public keys 6 and 8.

In another case, if X2 Xtto is excited by the output of More than the third comparison circuit 18, the potential of which passes through the elements OR 29 and 31, turns on the triggers 13 and 15 and thereby ensures the communication of information inputs 2 and 3 with information output 11 through public keys 7 and 9.

If it is necessary to disassemble the attached paths, a signal is applied to the input 32 of the assembly of the device, which is fed to the inputs of the installation in O from the first to the fourth flip-flops 12-15. Thereafter, a zero potential is fixed at the single outputs of these triggers, which closes all four switches 6-9 of the switching device.

In accordance with the indicated operation of a single switching device, it is not difficult to understand its operation when interacting with other similar devices.

The devices in the flat switching structure 51 of FIG. 3 when organizing parallel settings for non-single substitution. This type of substitution is supposed to be implemented before the exchange.

information between processors, which should automatically configure the flat switching structure 15 to the appropriate connection program. Thus, in the multiprocessor computing system of FIG. The 3 organizations of simultaneous, always non-blocking branching connections between the processors 47-50 are conducted from the side of the output poles to which the successive codes of the input poles 61 -64 are simultaneously exposed. 3, according to the substitution of the processors 47, exposes the pole code 82, the processor 48 the pole code e2, the processors 49 and 50 exposes the pole code ei. And these codes

The settings are selected by the length iog2 N, where N is the number of processors in the system.

At the same time, the corresponding processor on the diagonal of a flat switching structure is 51 using a feed

pulses to the inputs 33. 34 and 36 synchronization includes a group of their switching devices; Thanks to this, the wiring is a consistent, non-blocking push through of binary setup codes through

devices, crush (ommutations of a flat structure), in which these codes are compared both between themselves and with the setting code XT in the setting registers 22.

It is easy to estimate the setting time on

shown and implemented in FIG. 3 different substitution. So the first processor 47 for two clocks diagonally turns on the switching devices 37 and 38 in series, the second processor 48 also for

two clocks include diagonally switching devices 39, 40 and 41, 42, the third processor 49 switches switching devices 43-45, and the last processor 50 needs to include only device 46 in the first clock

switching, since its second is so; t is used to inform other processors about the end of the channel setup. Taking into account that in this case the time for pushing tuning codes is proportional to each switching device log2N, then the total non-blocking tuning time N for single and single connections does not exceed the estimate

TH (2N-1) log2N cycles.

Claims (1)

The invention The switching device containing the first to the fourth keys, the first to the fourth triggers, the first and second input registers, the first to the third elements AND, the first to the fourth elements OR, the first information input of the device connected to the information inputs of the first input register , the first and second keys, the second information input of the device to the information inputs of the second input register, the third and fourth keys, the reset input of the device connected to the installation inputs in O from the first The fourth trigger, the first synchronization input of the device is connected to the synchronization inputs of the first and second input registers, the outputs from the first to the fourth flip-flops are connected to the control inputs of the first to fourth keys, respectively, the outputs of the first and third keys form the first information output of the device, the outputs of the second and the fourth keys form the second information output of the device, distinguished by the fact that, in order to expand the scope of application by eliminating interlocking connections with parallel In addition to setting up a flat switching structure, it additionally contains a tuning register, the left and second NO-AND elements, the first and second NO elements, the first to fourth comparison circuits, the delay element, the second synchronization input of the device connected to the first gates of the first, second, and second the fourth comparison circuit, to the input of the delay element, the output of which is connected to the first gating input of the third comparison circuit, the output Equal to which is connected to the first input of the first and third OR elements, whose outputs .The inputs connected respectively to the setting to 1 the first and third flip-flops, the input device is connected to the tuning code infor mation entry setting register, whose output is connected to the first information input of the fourth comparison circuit, the output of the first register with the first information inputs from the first to the third comparison circuits and the inputs of the first NE-AND element, the output of which is connected to the first input of the third And element and to the input of the first NO element, the output of which is connected to the first inputs of the first and second elements And, the outputs of which are connected to the second gating inputs of the first and second comparison circuits, the output of the second input register is connected to the second information inputs of the second and fourth comparison circuits and the inputs of the third element are NOT-AND, the output of which is connected to the second input of the first element AND, and to the input of the second element NOT, the output of which is connected to the second inputs of the second and third elements AND, the output of the latter is connected to the second input of the gating fourth comparison circuit comparison is connected to the first inputs of the second and fourth elements OR, the Output More than the fourth comparison circuit - with the second input of the fourth element OR, the outputs Equal to the first and fourth comparison circuits are connected to the second inputs of the co respectively, the first and third elements OR, the output. Less than the second comparison circuit is connected to the third inputs of the first and fourth OR elements, the output of which is connected to the installation input of the 1st circuit trigger, the output. Equal to the second comparison circuit is connected to the second input of the third comparison circuit, the output is greater than the first comparison circuits - with the second input of the second OR element, the output of which is connected to the input 1 of the second trigger, the output of the setup register is connected to the second information inputs of the first and third circuits compared Yield more second comparing circuit connected to the second and third inputs tpeTbero element or third input synchronization device connected to the synchronization inputs of the first to fourth flip-flops. : 7iiH Fig2 fig.Z