SU1709304A1 - Device for calculating functions - Google Patents

Abstract

The invention relates to the field of computing and can be used in computer systems and streaming systems. The aim of the invention is to simplify. This goal is achieved in that a device containing a register 1, a memory block 7, an adder 8, quadrs 2, 4-6 multiplication and squaring blocks, six delay elements 3, 9, 10-13 are entered. 1 hp ff. Sil.i2a • CHONOCO4 ^ > & 8Lparameta IssuedJsext. Issuance of FIG. one

Description

The invention relates to computing and can be used in computer systems and streaming systems for the hardware implementation of a functionally complete class of elementary functions.

There are various methods of reproducing functions: polimial. Tabular-polimial; tabular algorithmic.

A device that implements table-polymial algorithms is known that contains a memory block, registers of the lower and higher parts of the argument, two summand registers, a multiplexer, an adder and a control block.

The disadvantage of the device is low accuracy.

A Toke device is known to contain a constant memory block, four registers and an adder.

This device implements a polimial algorithm, however, it has a very low speed due to the large number of multiplication operations and the series-parallel multiplication method, which is characterized by a significant multiplication time.

The closest in technical essence is a device containing two memory blocks, an address counter, two switches, two registers, two adders, a delay element, two multipliers, a decoder, a comparison circuit, an And element and a pulse generator, and a pulse generator through, And connected to the input of the counter, the output of which is connected to the input of the decoder and the comparison circuit, the first output of the decoder is connected to the first input of the first switch, and the second to the input of the first and second memory blocks and the first input of the second switch, The first and second outputs of the first switch are connected to the first and second outputs of the first multiplier, whose output is connected to the input of the first adder, the second input is connected to the third output of the first switch, and the third output to the first output of the second switch, the second and third outputs of which are connected to the first and second inputs of the second multiplication circuit, the output of which is connected to the first input of the second adder, and the second input is connected to the fourth output of the second switch, the output of the second adder is connected to the input of the second memory block.

The disadvantage of the device is a large consumption of equipment and low speed, due to the inability to work in the current mode. The purpose of the invention is to reduce hardware costs.

The goal is achieved by introducing a quad and three power and six multipliers into a device containing a memory block, an adder, a register.

delay elements, and the argument input is connected to the register input and the quad input, the quad output is connected to the first input of the first and through the first delay element to the first input of the second

0 multiplier and exponentiation units, the second input of the first multiplication and exponentiation unit is connected to the first register output, the third input of the first multiplication and exponentiation unit is connected to the quad output, the second input of the second multiplication and exponentiation unit is connected to the first output the first block of multiplication and exponentiation, the second output of which is connected to the third

0 the input of the second multiplication and exponentiation unit, the first and second inputs of the third multiplication and exponentiation unit are connected to the first and second outputs of the first multiplication and elevation flea degree, and the third input with the second output of the second multiplication and erection unit 8 degree, the second output of the register, the output of the quadrant, the first and second outputs of the first and second multiplication and raising blocks, respectively, through the first, second, third, fourth and fifth delay lines, and the first and second outputs of the third multiplication unit and The power is directly connected to the first, second, third, fourth, fifth, sixth, seventh, and eighth inputs of the memory block, the output of which is connected to the input of the adder.

In the device for. calculating functions

0, the multiplier and exponentiation unit contains two quadrs, a subtractor, an adder-subtractor and a delay line, the first and second outputs of the block are connected to the first and second inputs of the quad,

5 inputs are connected to the first and second inputs of the subtractor and the adder-subtractor, respectively, and the third input of the adder-subtractor is connected via a delay line with the third input of the device.

0 In known devices, parallel code is used and matrix multipliers must be used for exponentiation and multiplication. Depending on the speed required, their number may

5 vary. In the prototype, the polynomial is divided into two groups, which requires two matrix multipliers, i.e. 2 / n / 5p + 4 // elements I. In the proposed device, a sequential code is used and to build the device, the unit requires 7x / 7n + 1 /, i.e. in rj - -td- U, 2 n times less. At the same time, the speed of the device as a whole is not lower than in the prototype; For example, for (the degree of a polynomial) have 4tvM + 2tcvM 6 B 8 the proposed device, the result will be 14 formed after 14 g. I.e. t} - 2 3 times less. Fig. 1 shows a diagram of a device where register 1, quad 2, delay elements 3.9.10,11,12,13, block 4,5,6 multiplication and squaring, block 7 of memory, adder 8 are indicated. In this case input 1 device connected to the inputs of the register 1 and block squaring 2, the output of the squaring block is connected with the input of delay element 3, inputs 2 and 3 of the multiplication and squaring block 4, input 1, which is connected to the first output of register 1, and the delay element 9, the input of the delay element 3 is connected to the first input of the multiplication and squaring unit 5, the second and third inputs of which are connected to the first and second output of the multiplication and squaring unit, which are additionally connected to the first and second multiplication and squaring unit 6, to the delay elements 10 P1 11, the first and second outputs of the multiplying and raising unit square 5 is connected to the inputs of the delay elements 12 and 13, the second output is additionally connected to the third input of the multiplication and raising unit 6, the second output of register 1, the outputs of the delaying elements 10-13 and the first, second outputs of the multiplying and raising unit to degree 6 are connected respectively to the first and so on up to eight inputs of the memory block 7, the output of which is connected to the input of the adder 8, the control inputs of the nodes are connected to the input From the device.V. FIG. 2 is a block and multiplication block diagram. The block contains quadrants 14i and 142, calculator 14z, adder-calculate 144, delay element 145. FIG. Figure 3 shows a squaring scheme that includes a register 15, n of single-charge multipliers 16, and n combinational adders in a binary redundant code. 17 and t) -l commuting cells 18. The device operates as follows. Argument X is a sequential high-order bit leading to the input of register 1 and quadrant 2. At the output of the quad, the value x is formed. The result is output after the oval binary sign code, starting with the high-order bits. The digits {1, O, 1} are used to represent the bit. The coding of negative and positive units is spatial, i.e. a negative unit is transmitted on one bus and a positive one on the other, zero is encoded by the absence of signals on both wires. FIG. 1 outputs for simplified single wire circuits. And so the generated value x is fed to the first input of the multiplication and squaring block 4 (FIG. 2), the second input is the argument. Since in the quadrant the result is formed with a delay, then the arguments x to the input of block 4 do not come from the input, but from the first output of register 1, which ensures the required delay. In the first quad, the square of the sum of the input arguments is formed. In our case (x + x) + x. In which the squared difference (xx) + x. The output of the calculator is respectively formed (x + 2x + x - x + 2x - x 4x, and the output of the calculator-calculator is formed - the magnitude (x + 2x + x + x - 2x + x) - 2x 2x. The delay element 145 provides receipt of bits x synchronously with the formation of results at the outputs of quadrants 14i and 142 and multiplication x by 2. In the second multiplication and squaring block 5, a calculation is organized (x + x + 2x + x and (x - 2x + x, i.e. The values 4x and 2x are formed. In the third block b the values 4x and 2x are formed, respectively. The current bits of the values X, x, x, x, x, x, x, x are fed to the inputs of the memory block 17 through the delay elements, which ensure the arrival of bits with the same weights and together form the cell address.The next information is recorded in each cell. In other words, the sum of the coefficients of the polynomial L Aoh + aix + a2x + ax + a4x + is written in each cell. avx + abx + atx, each of which is multiplied by the current bit of the argument x, equal to {-1.0, 1}. After summing up the cell value with the contents of the adder, the result is shifted along the falling edge of the Co signal and the next bits of the degrees of the argument are calculated. After calculating all 9 bits on the adder, the value of the polynomial L is formed. The output can be performed in parallel code through n + 8 cycles or in sequential code through 8 cycles. In this case, the resulting high bit is not changed further and can be processed immediately.

FIG. 2 shows a block multiplication and squaring block diagram. The unit works as follows. Information from inputs 1 and 2 is fed to adders 14i and 142, while this information from input 2 is crossed, i.e. a subtraction operation is performed. After squaring, the results are summed at adder 145 and the sum through delay elements ensuring simultaneous output of information at the first and second outputs goes to output 1. At the adder 14b, the results of squaring are added together with the number of input to input 3. Since the delay of the adder 14b is higher than the adder 145. then it arrives at the output without additional delay.

 The squaring unit operates as follows. The initial number comes in a sequential redundant binary code, starting with the higher bits. The number of bits is (8, 16, etc.,). Ml sync pulses are built like this. what appears at the moment of passing the same-named bit (Ml at the moment of passing the first bit, Ml-second, etc.). The number of pulses M | may exceed the number of bits in multiples of I, for example, I 8, n 8, 16, 24, etc. This is related to squaring with the required accuracy. If, then with multiplicity I, the pulses appear at the same time, but in different cycles. For example, I 8 and p 32. Then MI appears in the first cycle of the first cycle. Ma appears in the first cycle, but the second cycle, Mn - the first cycle of the third cycle. Since all pulses are completed in the third cycle, the circuit returns to the initial state. The number of pulses (number of cycles) is determined by the required accuracy. For example, in the case under consideration, the number of subsequently included quadrators is four, then p 16. In the quadrant of the first stage, the following pulses will be used: at the first stage Mi-Mj, at the second stage -.

The construction in square is carried out as follows.

The first multiplier multiplies the first digit of the multiplier by all multiplicates of the multiplicand (in the case of a square, the multiplicand and the multiplier are equal), i.e. the first partial product is formed, the second multiplier is the second, and so on. The summation of the obtained partial products is carried out at adders 17i, 172 ... 17. Since the first bit is obtained in it with a delay per beat, the highest bit of the true work is obtained after two cycles, the first square is obtained with a delay of two cycles.

Since the information goes to the next square with a delay of two cycles,

in the quadrants of the next level, pulses are used: 1-stage Mz-Mu; 2-stage MS-MIi: on the third level 1-stage M5-Mi2: 2-stage My-Mia, fourth level 1-stage M7-M14; 2-

level MD-M 15.

Since all the pulses M are strictly synchronous with the series of Co, the equation of the registers is carried out precisely by the series of Co.

Suppose that a series of Co is submitted to the second level quadrant, but the information has not yet come up. Then even the signals of M. Recorded information in the register of the 15th quadrant is not processed (there are no signals M), then after the occurrence of a certain time it

pushed out of the register.

To ensure synchronous information following the Co series, delay lines 3,9,10,11,12,13 are used. providing simultaneous arrival of the same-named bits to the memory block strictly according to the signal of the Co series.

The delay can also be used to multiply, divide by a power of two. For example, if the first bit is in the first cycle, the second is in the second, and so on, then by setting the required delay line, you can achieve that the first bit goes through in the second cycle (division by two) or in the third (division by

four) etc.

Therefore, if it is possible to submit bits of the same name to the memory block, this indicates that the weights of these quantities are equal to one.

Estimation of equipment consumption. In the prototype, 2 matrix multipliers are used, which requires 2 (n (5p + 4) elements I.) The proposed device uses a sequential code and 7 () elements are needed to build the device,

those. 7 lp 0.2 times less.

In terms of speed, it will take five multiplications of six additions to compute a polynomial, i.e. in fact, Tpr 11t (addition time multiplication time g).

In our case, to determine the most significant bit, 12 cycles of squaring, 4 per unit of multiplication and squaring, i.e. only 12 and

tact for reading from memory and summation, Tvred. 16gt.e. j; that 1.4 more.

Formula and 3 assumptions. 1. A device for calculating functions comprising a memory block, an adder and a resistor, characterized in that, for the sake of simplification, it contains a quad, three multiplication and exponentiation blocks and six elements delay, and the input argument of the device is connected to the information inputs of the register and Quad, the output of which is connected to the input of the first operand of the first multiplication and raising unit and through the first delay element with the input of the first operand of the second multiplying and raising unit The second and third operands of the first multiplication and raising unit are connected respectively to the first register output and the quad output, the second operand input of the second multiplication and raising unit to the first output of the first multiplication unit and raising power, the second output of which is connected to the input of the third operand of the second multiplication and raising unit, the inputs of the first and second operands of the third multiplication and building unit are connected to the first and second outputs of the first Lok multiplication and exponentiation, the third operand input of the third multiplying unit and erected any degree - to the second output of the second

the multiplier and exponentiation unit, the second register output — with the first address input of the memory unit, the second to the sixth address inputs of which are connected respectively through the second to sixth delay elements, respectively, with the quad output, the first and second outputs of the first multiplication and exponentiation unit the first and second outputs of the second block

multiplying and raising to the power, and the second outputs of the third multiplying and raising unit to the power are connected to the seventh and eighth address inputs of the memory block, the output of which is connected to the information input of the adder, whose output is connected to the output of the device, the clock input of which is connected to the synchronization inputs the register, the first to the third blocks of multiplication and exponentiation, quad and adder. 2, The device is pop. 1. distinguished by the fact that each block; multiplying and raising to a power contains an adder-subtractor, a subtractor, two quadrants and an element

delays, and the inputs of the first and second operands of the block are connected to the first and second (the inputs of quadrants, the outputs of which are respectively the inputs of the first and second operands of the subtractor and the adder-subtractor, the outputs of which are connected respectively to the first and second lines of the block, the input of the third operand which is connected via a delay element to the control input of the adder-subtractor.

V.1

Out2

0g.2

Claims (2)

Claim 1. A device for calculating functions, 5 containing a memory unit, an adder and a register, characterized in that, for the sake of simplicity, it contains a quadrator, three units of multiplication and raising to a power and six delay elements, the input of the device argument 10 being connected with information inputs of the register and the quadrator, the output of which is connected to the input of the first operand of the first block of multiplication and raising to the power and through the first element 15 of the delay with the input of the first operand of the second block of multiplication and raising to the power, the inputs of the second and third the operands of the first block of multiplication and exponentiation are connected respectively. With the first output of the register and the quad output, the input of the second operand of the second block of multiplication and exponentiation is with the first output of the first block of multiplication and exponentiation, the second output of which is connected to the 25th input the third operand of the second block of multiplication and exponentiation, the inputs of the first and second operands of the third block of multiplication and exponentiation are connected respectively to the first and second outputs of the first block of multiplication and reduction to the power, the input of the third operand of the third block of multiplication and raising to the power - with the second output of the second block of multiplication and raising to the power, the second output of the register - with the first address input of the memory block, the second to sixth address inputs of which are connected respectively through the second-sixth delay elements, respectively, with the output of the quadrator, the first and second outputs of the first block of multiplication and exponentiation, the first and second outputs of the second block of multiplication and exponentiation, the first and second outputs of the third The multiplication and exponentiation blocks are connected respectively to the seventh and eighth address inputs of the memory block, the output of which is connected to the information input of the adder, the output of which is connected to the output of the device, the clock input of which is connected ^ to the register synchronization inputs, from the first to third multiplication blocks and exponentiation, quadrator and adder. 2. The device according to π. 1 characterized in that each unit of multiplication and exponentiation contains an adder-subtractor, a subtracter, two quadrators and a delay element, and the inputs of the first and second operands of the block are connected to the first and second inputs of the quadrants, the outputs of which are respectively the inputs of the first and second operands a subtractor and an adder-subtractor, the outputs of which are connected respectively to the first and second outputs of the block, the input of the third operand of which is connected via a delay element to the control input of the adder-subtractor. No. X X * X ' χ ^ Cell contents 1 00 00 00 00 00 00 00 00 0 + 0 + 6 + 0 + 0 + 0 + 0 + 0 = 0 1 10 00 00 00 00 00 00 00 ao + 0 + 0 + ... +0 = 3ο 2 λ 01 00 00 00 00 00 00 00 ao + 0 + O. . . + 0 = -a _o ίό όί όί όό όί ίό 00 ίό Eo * E1 - E2 + 0 - E4 + as +0 - E7 2 10 10 10 10 10 10 10 10 ao + ai + ar + a s + a 4 + as + a b + a v.