SU1707789A1 - Resistive element tester - Google Patents

Abstract

This invention relates to radio engineering and can be used in analog integrated filters. The purpose of the invention is to improve accuracy. The device contains an adjustable differential resistive element (DDR), an operational amplifier with a differential input and a balanced output, a reference voltage source with a balanced output, first and second adjustable current sources and a control unit of adjustable current sources. The latter contains the first and second equivalents of resistors made on the first and second switched capacitors, an operational amplifier and three transistors. In addition, the device contains a two-phase clock pulse generator and two integrating capacitors. The principle of operation of the device is based on the alignment of the resistances of the switched capacitor and ECD. 1 hp f-ly, 3 ill.

Description

WITH

with

This invention relates to radio engineering and can be used in analog integrated filters.

The purpose of the invention is to improve accuracy.

Figure 1 shows the functional diagram of the device together with elements of an analog integrated MOSFET from the filter; Fig. 2 is a circuit diagram of a control unit of controlled current sources; FIG. 3 shows diagrams of two phases of the control clock signal.

The device (Fig. 1) contains an adjustable differential resistive element 1.1, made on the first 2.1, second 2.2, third 2.3 and fourth 2.4 MOS transistors, unit 3 of the control of adjustable current sources made on

the first switched capacitor 4.1, differential amplifier 5 charge, made on the operational amplifier 6 with a differential input and balanced output 8, the first 7.1 and second 7.2 integrating capacitors, a two-phase generator 9 clock pulses, a reference voltage source 10 with a balanced output, the first 11 and the second 12 adjustable current sources, and the drain (source) and source (drain) of the first MOS transistor 2.1 are connected respectively to the drain (source) of the second MOS transistor 2.2 and drain (source) of the third MOS transistor 2.3 and are variable differential pair of terminals of the resistive element 1.1, the source (drain) and the drain (source) of the fourth MIS transistor connected sootvetstVI 2.4

about VI VI

00

about

However, the source (drain) of the second differential resistive element 1.1, the substrates of the first 2.1, second 2.2, third 2.3 and fourth 2.4 MOS transistors are connected to the first power bus, the gates of the first 2.1 and fourth 2.4 MIS transistors are connected to the second power bus, the second gates 2.2 and the third 2.3 MIS transistors are combined and are the control input of the adjustable differential resistive element 1.1. The first integrating capacitor 7.1 is connected to the negative feedback circuit of the operational amplifier 6, and the second integrating capacitor 7.2 is connected to the negative feedback antiphase circuit. The balanced outputs of the source 10 of the reference voltage through the adjustable differential resistive element 1.1 are connected to the differential input of the differential charging amplifier 5, the output of which is connected to the control input of the adjustable differential resistive element 1.1 and is the output of the device, the balanced outputs of the source 10 of the reference voltage are connected to the differential the input of the control unit 3 controlled current sources, the first and second outputs of which are connected to the control inputs, respectively 11th and second controlled current sources 12, included between the second bus and the input power of the amplifier 5 the charge, and the first power bus and antiphase input charge amplifier 5, respectively. In addition, the device contains an analog filter 13, made on the second, third, ..., Nth adjustable differential elements 1.2, 1.3, ..., 1. N, matched with the first adjustable differential element 1.1, the control input of which is connected to the output of the amplifier 5 charge, the second, third ...., Mth capacitors 4.2,4.3 ..., 4. M agreed with the first switched capacitor 4.1.

The device (figure 2) contains the first and second equivalents of resistors made respectively on the first 4.1 and second 4.M + 1 switched capacitors, operational amplifier 15. non-inverting input 14 of which is connected to a common bus, and inverting input through the third integrating capacitor 16 is connected with the output and the gate of the fifth MOS transistor 17 of the opposite conductivity type, with the first MOS transistor and the first output of the control unit of controlled current sources, the source and the substrate of the fifth MOS transistor 17 are connected to the second power bus, and the drain is connected to the gate and drain of the sixth 18 and gate of the seventh 19 MIS transistors and is the second output of the control unit

regulated current sources, sources and substrates of the sixth 18 and seventh 19 MOS transistors are connected to the first power supply bus; the drain of the seventh MOS transistor 19 is connected via the first switch 20 to the common

0 bus, and through the second key 21 is connected to the first output of the third key 22 and the first output of the second switched capacitor 4.M + 1. the second pin of which is connected to the common bus and the first pin

5 of the fourth key 23, the second output of which is connected to the first output of the fifth key 24 and through the first switched capacitor 4.1 is connected to the first output of the sixth 25 and the first output of the seventh 26

0 keys, the second terminal of which is connected to the second terminal of the third key 22 and the inverting input of the operational amplifier 16, the second terminals of the fifth 24 and sixth 25 keys being the differential input of the device, the control inputs of the second 21, the fifth and sixth 25 keys are connected generator 9 clock pulses, anti-phase output of which is connected to the control inputs

0 first 20, third 22, fourth 23 and seventh 26 keys.

The device (figure 1) works as follows.

The well-known principle of equalizing the resistances of a switched capacitor (QC) and a controlled resistor is used. Since the resistance of QC is equal (Сртт), where CR is the capacity of QC. fj is the switching frequency of the QC, then, equating it to the resistance of the controlled resistor R.

(CRfy) 1 R or RS Pcs (1)

From the expression (1) it can be seen that

RCR time is equal to the period

5 clock frequency with which the commutated QC. Since the clock frequency can be generated by a reference clock pulse generator (e.g., a quartz oscillator), the absolute value error

0 constant RCs are determined by the frequency setting error of the reference clock.

Since the voltage at the outputs of the source 10 of the reference voltage is not equal to

5 to zero, then currents flow through the adjustable differential resistive element 1.1. At the same time, currents begin to flow through the first 11 and second 12 regulated current sources due to their supply to the control inputs of the signals from the outputs

control unit 3. Taking into account the direction of the currents flowing through the adjustable differential resistive element 1.1 and the first 11 and second 12 adjustable current sources, it can be concluded that in the case of inequality of these currents between themselves, the first 7.1 and second 7.2 integrating capacitors are charged by differential currents. For this reason, if the current flowing through the adjustable differential resistive element 1.1 to the non-inverting differential input 6 is less than the current flowing through the first adjustable current source 11, then the differential current charges the integrating capacitor 7.2. This will cause the voltage on inverting output 8 to decrease, thereby causing a decrease in resistance of the adjustable differential resistive element 1.1. For this reason, the current through it increases until it exits until it is comparable with the current of the first controlled current source 11. At this moment, the currents through the integrating capacitors 7.1 and 7.2 cease to flow and a control voltage Vc is established on them, which leads to a controlled set value of the time constant r RCR.

Claims (2)

Claim 1. Device for controlling the resistance of a resistive element, containing an adjustable resistive element made on the first MOS transistor, the first equivalent of a resistor made on the first switched capacitor, a charge amplifier made on the operational amplifier, the negative feedback circuit of which is included the first integrating capacitor, a clock pulse generator and a voltage source, the output of which is connected through a pair of terminals of the adjustable resistive element To the input of the charge amplifier, and the first and second phases of the clock pulse generator are connected to the corresponding switching frequency control inputs of an equivalent resistor, characterized in that, in order to improve accuracy, the first and second adjustable current sources and the control unit of the adjustable current sources are additionally introduced into it. made on the first equivalent of the resistor, and the adjustable resistive element is differential and supplemented by the second, third and fourth MOS transistors of the same conductivity type and with the first MOS transistor: rum, with the drain (source) and source (drain) of the first MOS transistor connected to the drain (source) of the second MOS transistor and the drain (source) of the third MOS transistor, respectively, and are a pair of pins of the adjustable differential the resistive element, the source (drain) and drain (source) of the fourth MOS transistor are connected respectively to the source (drain) of the third MOS transistor and the source (drain) of the second MOS transistor and are 0 an antiphase pair of leads of an adjustable differential resistive element, the substrate of the first, second, third and fourth MOS transistors are connected to the first power supply bus, the gates of the first and 5 fourth MOS transistors - with the second power bus, the gates of the second and third MOS transistors are combined and are the control input of the adjustable differential resistive element, the charge amplifier is differential and made on a specific amplifier with a differential input and a balanced output, in antiphase the negative feedback circuit of which is included 5 a second integrating capacitor, wherein the source of the reference voltage has a balanced output, which through an antiphase pair of terminals of the adjustable differential resistive element 0 is connected to the antiphase input of the charge amplifier, the output of which is connected to the control input of the adjustable differential resistive element and is the output of the device, balanced The 5 outputs of the reference voltage source are connected to the differential input of the control unit of adjustable current sources, the first and second outputs of which are connected to the control inputs of the first and second adjustable current sources, respectively, connected between the second power bus and the input of the charge amplifier, and the first power bus and antiphase amplifier input, respectively. five 2. The device according to claim 1. that is, so that the control unit of the controlled current sources contains the first and second equivalents of resistors made respectively on the first and second switched capacitors, the operational amplifier, the non-inverting input of which is connected with the common busbar, and the inverting input through the third integrating capacitor is connected to the output and the gate of the opposite MOSFET transistor of the opposite conductivity type with the first MOS transistor and is the first output of the control unit The current source, source, and substrate of the fifth MIS transistor are connected to the second power bus, and the drain is connected to the gate and drain of the sixth MOS transistor and the gate of the seventh MOS transistor and is the second output of the control unit of controlled current sources, sources and substrates of the sixth and seventh MOS transistors connected to the first power bus, the drain of the seventh MIS transistor is connected through the first switch with the common bus, and through the second key is connected to the first output of the third key and the first output of the first switched capacitor, the second output of which is connected to the common bus and the first output of the fourth key, the second output of which of soybeans five dinene with the first output of the fifth key and through the second switched capacitor is connected to the first output of the sixth and first output of the seventh keys, the second output of which is connected to the second output of the third key and the inverting input of the operational amplifier, the second outputs of the fifth and sixth keys are the differential input devices, control inputs of the second, fifth and sixth keys are connected to the output of the clock generator, the antiphase output of which is connected to the control inputs of the first, third, fourth and the seventh keys. Phie.1 FIG. 2