SU1707740A1 - Digital non-recursive filter - Google Patents

Abstract

The invention relates to digital technology and can be used in systems for the digital processing of radio signals. The purpose of the invention is to improve the quality of filtering by lowering the side lobes of the frequency response of the filter in the notch band while maintaining a small unevenness of the frequency response of the filter within the passband / The device consists of a delay register 1, seventeen blocks 2 delay registers, sixteen adders 3 and a subtractor 4 connected to the corresponding switching binary bits The device allows to obtain a significantly lower relative level of side lobes of the frequency response in the notch band, equal to -100 dB.1il. fe vj o vj vj &

Description

The invention relates to digital technology and can be used in B systems for digital processing of radio signals.

Known digital non-recursive filter (CNF), which contains a block of registers of delays of samples of the input signal for the sampling period, in which the outputs of the registers of delays are connected to the inputs of the adder via multipliers of samples of the filter coefficient 1.

The disadvantage of such a device is the presence of multipliers that reduce the speed of the device and prevent the device from implementing a chip in the form of a large integrated circuit (LSI).

The known CNF contains the first and second filtering blocks connected in series, the first filtering block containing M delay registers and M adders connected in an appropriate way, and the second filtering block containing the first and second delay register blocks consisting of M registers and (M + 1) and (adders 2.

This device does not contain multipliers, which provides a higher speed and the ability to implement it in the form of an LSI.

However, in the CNF of this structure, it is impossible to obtain a low relative level of amplitude-frequency characteristic (AFC) in the notch band. which is close to the notch frequency is of the order of -13 dB.

The closest in technical essence to the proposed is the CNF on the delay registers, adders and subtractors x 3.

A disadvantage of the known device is the low filtration quality, due to the fact that its frequency response has a high relative level of side lobes in the notch band, which is not less than -37.5 dB. This limits the use of the known CNF.

The aim of the invention is to improve the quality of filtration by reducing the level of side lobes of the frequency response of the CNF in the notch band while maintaining a small unevenness of the frequency response within the passband,

The goal is achieved by the fact that a digital filter containing successively connected first and second blocks of delay registers, serially connected third and fourth blocks of delay registers, a first adder, the first input of which is combined with the input of the first block of registers and is an information input of a digital filter , the second adder, the first input of which is connected to the output of the first block of registers, the third adder connected in series, the fourth adder, the fifth block of delay registers, the fifth sum the torus, the sixth block of the delay registers and the sixth adder, another input of which is connected to the output of the fifth adder, another input of which is connected to the output of the fourth adder, and the seventh block of the delay registers, the input of which is combined with the first input of the seventh adder, the eighth block of the delay registers, the output of which is connected to the first input of the eighth adder, the ninth block of delay registers, the tenth block of delay registers and the series-connected ninth, tenth, eleventh adders and a subtractor, the output of which Is the output of a non-recursive digital filter, additionally introduced from the eleventh to the seventeenth blocks of the delay registers and from the twelfth to the sixteenth adders, with the 1st (I P7. M - bit) the bit of the output of the second block of registers is combined with the 1st bit of the first input and (1-4} th bit of the second input of the twelfth adder, the output of which is connected to the first input of the third adder, the third block of registers is connected to the output the second block of registers and the output of the third block of registers are connected to the PTOPO V input of the second summation; the i-th bit of the output of which is combined with the i-th bit of the first input and 0-4} th bit of the second input of the thirteenth summases. the output bit of which is connected to the () th bit of the second input quarter The output of the fourth block of registers is connected to the second input of the first adder, the i-th bit of the output of which is connected to the 0-2) -th bit of the second input of the third adder, between the output of the sixth adder and the seventh block of registers are connected in series the eleventh block of registers , the fourteenth adder, the twelfth block of registers, the fifteenth adder, the thirteenth block of registers, the sixteenth adder, the second input of the fourteenth adder is connected to the output of the sixth adder, and the output is connected to the second input of the fifteenth Ummator, the output of which is connected to the second input of the sixteenth adder, the seventh, eighth, ninth, tenth, fourteenth, fifteenth, sixteenth and seventeenth blocks of registers are connected in series, with the 1st bit of the output of the tenth block of registers connected to (1+ 4) the first bit of the first input of the ninth adder, the output of the nth block of registers is connected to the second input of the eighth adder, and the output of the seventeenth block of registers is connected to the second input of the seventh adder, the output of which is connected to the second input of the ninth adder, 1- the bit of the eighth adder is connected to (1 + 3) -th bit of the second input of the tenth adder and (1 + 5) cgu of the second input of the eleventh adder, the 1st bit of the output of the ninth adder is connected to (1 + 3} md non-inverting input of the subtractor.

The drawing shows a block diagram of the filter.

The digital non-recursive filter contains a register of 1 delay, seventeen blocks of 2.1-2.17 delay registers, sixteen adders 3.15-3.16 and a subtractor 4, while the information input of block 2.1 is an information input of a non-recursive filter and connected to the first input of adder 3.1. the second input of which is connected to the output of block 2.4, the output of block 2.1 is connected to the first input of adder 3.3, the second input of which is connected to the output of block 2.3. The 1st (I 1 .M, M is the size) output of the block 2.2 is connected to the lth bit of the first input and (K4) the second bit of the second input of the adder 3.4, the output of which is connected to the second input of the adder 3.5, (+2) -th bit of the first input of which is connected to the l-th bit of the output of the adder 3 1 1-th bit of the output of the adder 3.3 is connected to the i-th bit of the first v / s-de and (I- 1) - m bit of the second adder 3.2. The i-th bit of the output of which is connected to (i 12} -th bit of the second input of the adder 3 6. The first input of which is connected to the output of the adder 3.5. The output of the adder 3 6 is connected to the input of the unit 2.5 and the output of the adder 3.7, the second input of which connected to the house of the block 2.5. The output of the adder 3J (J 7.11) is connected to the input of the block 2.J-1 and the first input of the adder 3.J-1-. The second input of the adder 3.K (K 8.11) is connected to the output 2.K-2 block, the second input of the adder 3.12 is connected to the output of the block 2.17, the output of the block 2.11 is connected to the first input of the adder 3.13, the second input of which is connected to the output Lock 2.15, the 1st bit of the output of the block 2.13 is connected to (+4} oasr of the first input of the adder 3.14, the second input of which is connected to the output of the adder 3.12.1, the th bit of the output of the adder 3.13 is connected to (+3) - m bit of the first input of the adder 3.15 and (1 + 5) -m bit of the first input of the adder 3.16, the output of which is connected to the inverting input of the subtractor 4.1,1 bit of the output of the adder 3.14 is connected to the 1st

the bit of the second input of the adder 3.15 and (K3) is the bit of the non-inverting input of the subtractor, the second input of the adder 3 16 is connected to the output of the adder 3.15. output

5, the subtractor is the output of the CNF.

The filter works as follows. For each clock sync pulse arriving at the clock inputs of blocks 2.1-2.17 of the registers,

0 write the next process sample to the register 2.1. At the same time, the binary information is shifted in blocks 2.2-2.4, 2.10-2.17 of registers, and information is updated in blocks

5 2.5-2.9 registers. Upon completion of the transient processes in the combinational totalizers 3.1-3.16 and the subtractor, the corresponding binary codes are set at the inputs of blocks 2.5-2.10 of the registers, which determine the state of these registers at the next operation cycle, and the binary code corresponding to the output value of the output process is set at the output of the subtractor 4 filter at the time in question

5 work. The frequency response of the proposed filter is described by the expression

/ H (QTy / ((8-cos2 QT +

0 H-24 cos QT + 17 (14-COS4 QT - -80 cos 2 QT + 112) | 32

where T L D T is the operation cycle of the digital filter;

5L - the number of delay registers in each of the blocks 2.1-2.17 (1 1.2 ...).

Thus, preserving the main advantages of the prototype - high speed and low hardware

0 costs (obtained due to the absence of multipliers in the composition of the device), the proposed device is advantageously characterized by higher quality filtering. This allows for a wider range of use.

Claims (1)

5 and ensure its implementation in the form of LSI. The invention includes a digital non-recursive filter containing serially connected first and second blocks of delay registers, 0 serially connected third and fourth blocks of delay registers, the first adder, the first input of which is connected to the input of the first block of registers and is the information input of a digital 5, the second adder, the first input of which is connected to the output of the first block of registers, the third adder, the fourth adder, the fifth block of the delay registers, the fifth adder. the sixth block of delay registers and the sixth adder, another input of which is connected to the output of the fifth adder, another input of which is connected to the output of the fourth adder, and the seventh block of delay registers whose input is combined with the first input of the seventh adder, the eighth block of delay registers, whose output connected to the first input of the eighth adder, the ninth block of the delay registers, the tenth block of the delay registers and the series-connected ninth, tenth, eleventh adders and a subtractor, the output of which is The output of a non-recursive digital filter, characterized in that, in order to improve filtering quality by lowering the relative level of the frequency response of the filter in the notch band while maintaining a small relative non-uniformity of the frequency response of the filter within the passband, the eleventh through seventeenth delay register blocks and c are added to it the twelfth psgsteenteenth adders, while the 1st (1 1 .M, M is the bit) the output bit of the second block of registers is combined with the 1st bit of the first input and (K4) -th bit of the second output the twelfth adder, the output of which is connected to the first input of the third adder, the input of the third block of registers is connected to the output of the second block of registers, and the output of the third block of registers is connected to the second input of the second adder, the 1st discharge of which is combined with the first discharge of the first input and (1 + 1) -th bit of the second input of the thirteenth adder, the 1st bit of the output of which is connected to () -th bit of the second input of the fourth adder, the output of the fourth block of registers is connected to the second input the sixth adder, the 1st bit of the output of which is connected to (I + 1} th bit of the second input of the third adder, between the output of the sixth adder and the input of the seventh block of registers are connected in series the eleventh block of registers, the fourteenth adder, the twelfth block of registers, the fifteenth adder, the thirteenth block of registers, the sixteenth adder, the second input of the fourteenth adder is connected to output of the sixth adder, and the output with the second input of the fifteenth adder, the output of which is connected to the second input of the sixteenth adder, the seventh, eighth, ninth, tenth, fourteenth, fifteenth, sixteenth and seventeenth blocks of registers are connected in series, with the 1st the bit of the output of the tenth register block is connected to (K4} th bit of the first input of the ninth adder, the output of the fifteenth block of registers is connected to the second input of the eighth adder, and the output of the seventeenth block of registers to the second input of the seventh adder a, the output of which is connected to the second input of the ninth summator. The 1st bit of the output of the eighth adder is connected to (K3) -th bit of the second input of the tenth adder and (1 + 5) -th bit of the second input of the eleventh adder, 1 the th bit of the output of the ninth adder is connected to the (K3) th bit of the non-inverting input of the subtractor.