SU1705757A1 - Frequency sensor parameter measuring device - Google Patents

Abstract

The invention can be used to measure parameters of frequency sensors and in systems of automatic control of parameters. A device for measuring parameters of frequency sensors contains first and second counters 15, 16 pulses and a generator 14 clock pulses. Introduction of frequency sensors 1, frequency-code converters 2, block dividing unit 3, blocks 4, 5. 6 multiplication, adder 7 numbers, blocks 8, 9, 10, 11 of memory of switches 12, 13. trigger 17, switch 18 and registers 19 and extends the functionality and accuracy of the device. 1 hp f-ly, 3 ill.

Description

Vj o

ate VJ

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Vj

The invention relates to information measuring systems and can be used to measure pressure, volumetric flow rate of liquids and gases, angular velocity, as well as other parameters converted by primary converters into a frequency-pulse form.

The purpose of the invention is to improve the accuracy of the device and expand its functionality.

FIG. 1 shows the functional electrical circuit of the device; in fig. 2 - frequency-code converter circuit; in fig. 3 - diagrams of the following measurement and reference pulses, explaining the principle of its action.

The device contains frequency sensors 1-1 ... 1-p, converters 2-1 ... 2-p frequency-code, block 3 division codes, first-third block 4-6 multiplication of numbers, adder 7 numbers, first-fourth blocks 8-11 of memory, first and second switches 12 and 13, generator 14 clock pulses, first and second counters 15 and 16 pulses, trigger 17, switch 18 and registers 19-1 ... 19-p.

The outputs of the frequency sensors 1-1 ... 1-p are connected to the first inputs of the respective converters 2-1 ... 2-n frequency-code, the first information outputs of which are combined at the first inputs of the block 3 division of codes, and their second information outputs - on the second inputs of this unit 3 division codes, respectively, whose outputs through the first block 4 multiply numbers are connected to the first and second information inputs of the second and to the first information inputs of the third blocks 5 and 6 multiply numbers, the outputs of which are connected to the first and second information and inputs of the adder 7 numbers, respectively, the output bus of which is connected to the input buses of registers 19-1 ... 19-p, the write inputs of which are connected to the corresponding outputs of the bits of the second switch 13, the input bus of which is connected to the output bus of the second counter 16, input tires of the first to fourth memory blocks 8-11 and the input bus of the first switch 12, the control input of which is connected to the control input of the dividing unit 3 and the output of the switch 18, and the 1-n-outputs to the second inputs of the respective converters 2-1. .2-hh simplicity code synchronizing outputs are connected to the second input flip-flop 17, whose output is connected to a control input of the switch 18, the generator output clock 14

pulses connected to the summing input of the first counter 15 pulses, the first and second outputs of which are connected to the corresponding inputs of the switch

18, the second and fourth with the control inputs of the first and third multiplication blocks 4-6, respectively, and the fifth with the control input of the adder 7, the first input of which is connected to the output bus of the fourth memory block 11, the output of the second memory block is connected with the second input of the first multiplication unit 4, the overflow output of the first counter 15 is connected to the first input of the trigger 17, the zeroing input of the first

5 of the counter 15 and the summing input of the second counter 16, the overflow output of which is connected to the zero input.

Each of the converters 2-1-2-p contains a shaper 20 pulses.

0 counter 21 pulses of the measured frequency, primary and secondary counters 22 and 23 pulses of the reference frequency, elements 24 and 25, triggers 26 and 27, generator 28 of the reference frequency, switch 29, elements 5 and 31 of the delay, registers 32 and 33, a match unit 34, memory blocks 35 and 36, and switch 37.

The converter input is connected via a pulse shaper 20 to the summing input of the pulse counter 21 of the measured frequency and the first input of the AND 24 element, the second input of which is connected to the trigger output 27, and the output to the first input of the first trigger 26 and through the first

5 delay element 30 — with inputs for recording registers 32 and 33 with the first input of the second element I 25 and the input of the second delay element 31, the output of which is connected to the zero input of the counter 21 pulses of the measured frequency, with the initial setup input of the counter 22 pulses of the reference frequency and the first input of the second trigger 27, the outputs of the generator 28 of the reference frequency through connected in series

5, the switch 37 and the switch 29 are connected to the summing input of the counter 22 pulses of the reference frequency and to the subtractive input of an additional pulse counter 23, the loan output of which is connected to

0 the input of the initial installation of this counter 23 and with the second input of the first trigger 26, the output connected to the control input of the switch 29, the information outputs of the counter 21 pulses measured

The 5 frequencies are connected via the first register 32 to the first information outputs of the converter, the information outputs of the counter 22 pulses of the reference frequency are connected to the first inputs of the matching element block 34 and through the second register 33 to the second information outputs of the converter, the outputs of the first memory block 35 are connected to the information inputs a counter 22 pulses of the reference frequency and an additional counter 23 pulses; the outputs of the second memory block 36 are connected to the second inputs of the block 34 of coincidence elements, the output cat The first is connected to the second input of the second flip-flop 27, and the output of the read control of the converter is connected to the read inputs of registers 32 and 33 and the second input of the second element And 25, the output of which is the synchronizing output of the converter.

Sensor 1-1 is, for example, for measuring pressure PI. Its characteristic is written in the general case by a polynomial of the 2nd degree:

Pi- Aafxi + Aifxi + AO,

0)

where PI is the current values of the measured parameter;

Aa, Ab AO - the polynomial coefficients, approximating the characteristic of the frequency sensor.

The second channel is intended, for example, to measure the volumetric flow rate of a liquid.

Qi B2fxl + Blfxl + Bo.

(2)

where QI is the current volumetric flow rate:

fxi is the frequency of the measuring signal generated at the output of the TPD 1-2 (measured in the range from 30 to 500 Hz);

Bz, BL V o - coefficients, approximating the flow characteristics of the sensor 1-2.

The last measurement channel is designed, for example, to monitor the speed of the drive and is equipped with a 1-speed pulse sensor with the number of inserts equal to Z.

When using the device in information display systems, the outputs of registers 19-1., 19-n are connected to the inputs of the display unit, and in other versions of its application, for example, in automatic control systems, to the inputs of the corresponding measurement information processing elements.

The device works as follows.

Preliminary adjustment of its circuit elements to the mode of operation, which ensures the smallest error in the conversion of measuring

signals to the code, based on the selected capacity of the counters 21, 22 and the expected range of generated frequencies fx (1 ... n). To do this, set the duration Gh (1 ... n) of measuring cycles for each of the measuring channels.

During the time rx, the counters 22 converters 2-1 ... 2-n should be maximally filled with pulses of the reference frequency fa, i.e.

fa (1 ... n) Tx (1 ... n) S (241-1)

(3)

where qi 16 is the number of bits of the counter 22 pulses.

On the other hand, for the same time interval mx, the counter 21 should read no more (2 h2 - 1) pulses of the input signal fx (1 ... n), i.e.

rx (l ... n) fa (l..n) s (242-1), (4)

where q2 8 is the number of bits of the counter 21 pulses;

fx (1 ... n) is the maximum value of the measured frequency.

From the relation (4) receive

2 P2 1

M1-) ЗоЗГГ

and the ratio (3) takes the form

(five)

35

 o-) Јтт5г) 6

from where

4i) f ffMi ---). YU

For the 1st measuring channel fxinaicc - 8 kHz and the calculated value of the reference frequency, obtained from relation (7), will be 2.048 MHz. From the number of fixed frequencies generated by the generator 28, fsi is chosen to be -2.0 MHz and switch 37 of the converter 2-1 is set at position 7.

The calculated duration of the measurement cycle rxi for the 1st channel according to equation (3) is equal to

Gx1 2S

216-1 2 106

 0.032 seconds

During this time interval, the generator 28 generates Mc1 pulses of the reference frequency fai:

Mts1-2 106 -0,032 64000 imp. 5

The code value of the Nui number is written to the memory block 36 of the converter 2-1.

For the 2nd measuring channel fx2Ma c - 500 Hz and the calculated value of the reference 10 frequency is 128 kHz. Select f92-125 kHz and set the switch 37 of the converter 2-2 to position 3.

The estimated duration of the GX2 measuring cycle for this channel15

Tx2

216-1 125 10

s 0.524 s

Take Gh2 equal to 0.4 s. Then Mts2 -125 103 0.4 50000 imp.

The code value of the number Mc2 is written to the memory block 36 of the converter 2-2.

Setting the 2-p converter with the number of inserts Z of the pulse sensor 1-p speed equal to, for example, six fxnMaKc 600 Hz (, similar to the 2-2 converter, i.e. fan - 125 kHz; ghp 0.4 s; Mcp 50 thousand pulses.

In memory blocks 35 of converters 2-1 ... 2-n, NH (1 ... n) codes are written, which are read by pulses of the reference frequency fa (1 ... n) during a time slightly longer than the total tuning time of the elements 30 and 31 delays and switching counters 22 to the initial state.

In memory block 8, the values of the selected frequencies fai are read. fa2, fa3, etc .. including fan, and in blocks 9,10 and 11 - sequences of coefficients A, B2 ... C2, Ai, Bi ... Ci and AO, Voo ... Co performance characteristics of sensors 1 -1, 1-2 ... 1-p, and for the n-th measuring channel, the coefficients C2 and C0 are equal to zero, and the coefficient Ci is determined by the formula

Ci rpm (8)

In the initial state, the pulse counter 15 and the trigger 17 are reset, the switch 18 is set to the position in which its output is connected to the first output of the counter 15, the first address code is formed at the outputs of the counter 16, according to which the switches 12 and 13 are transferred to the first the position and the outputs of the blocks 8-11 of the memory read the values of the reference frequency fai and, accordingly, the coefficients A2, Ai, AO of the calibration characteristic of the sensor

0

five

0

50

five

0 5

0 5

1-1. In the converter 2-1 ... 2-p elements And 24 and 25 are closed; the outputs of the flip-flops 26 and 27 are zero, the outputs of the switches 37 are connected to the summing inputs of the counters 22, the registers 32 and 33 contain arbitrary information.

Converters 2-1 ... 2-p work asynchronously with respect to each other and other circuit elements. For example, at an arbitrary time ti (Fig, 3), the counter 21 of the converter 2-1 is filled with pulses of the input signal fxi, and the counter

22 - pulses of the reference frequency f9i. When the Nui pulse is read into the last, an electrical signal is formed at the output of the block 34 of elements, which corresponds to a logical unit, which sets trigger 27 to one state and opens element 24 (time t2). As a consequence, the next pulse signal, excited at the output of driver 1 at time t3, not only increases the contents of counter 21, Noah, the passage through open element 24, changes the state of the trigger 26 connected to its output, switch 26, and 23, etc., namely: the trigger 26 is set to one state and through the switch 29 connects the output of the generator 28 to the subtractive input of the additional counter 23; the latter starts to work in subtraction mode, and the counter 22 stops; at a time interval equal to the setting of the delay element 30 and sufficient for the transient to pass in the counter 21. associated with recording the last measurement pulse in it, its contents tX1, as well as the contents of the counter 22, are written to registers 32 and 33; after the time interval corresponding to the setting of another delay element and sufficient for stable switching of the specified registers, a pulse signal is generated at its output, which resets the counter 21 and writes the initial set code NH1 stored in the main counter 22 stored in the memory of block 35; when reading the contents of the counter

23 to zero, at its output a transfer signal is excited as a logical unit that is addressed to the input of the trigger 26 and to its S input; at this command, trigger 26 is zeroed, resetting switch 29 to its initial state, and counter initial control code NH1 is rewritten to counter 23.

Next, the counter 22 is re-activated, and its accumulation of pulses of the reference frequency fai is not performed.

with zero, and taking into account the initial setpoint NH1 and the measuring cycle is repeated.

Converters 2-2 ... 2-p work in a similar way. Each of them organizes a sequence of measuring cycles, duration gx (2 ... n). which ranges from mx (2 ... n) to gx (2 ... n) + TX (2 ... n), accumulates in each cycle the incoming pulses of the input signal fx (2 ... n). and the results obtained here are read into register 32 as binary codes mx (2 ... n). At the same time, the number Nx (2 ... n) pulses of the reference frequency f3 (2 ... n) is written to another register 33. Allocated by the generator 28 for the time ghr ... n).

The processing of the measurement information generated by the converters 2-1., 2-n is performed by the commands of the counter 15 operating in a cyclic mode. When the first pulse of frequency fT is read into it, an electrical signal is excited at its 1st output, corresponding to a logical unit, which through switch 18 is addressed to the control input of unit 3, and through switch 12 to the control input of converter 2-1. At this command, the contents of registers 32, 33 are read into block 3, which divides the code mxi by the number Nxi of the accumulated pulses of the reference frequency fai:

A3

 mxi

Nxi

(9)

If the moment of outputting information from converter 2-1 coincides with the end of the measuring cycle and writing new registers mxi, NX1 to registers 32 and 33, an AND 25 element opens and a pulse signal appears on the synchronizing output of converter 2-1, which translates trigger 17 in one state, connect the output of the switch 18 to the second output of the counter 15.

The voltage pulse excited on it is again addressed to the control input of the converter 2-1 and the control input of unit 3 for duplicating the division operation of the codes mxi and Nxi.

By the command generated at the 3rd output of the counter 15, block 4 multiplies the number P3 (9) by the frequency, the value of which is read from the output of memory block 8. The product P3Te1 is equivalent to the desired frequency of the input signal

", -P, - mxi fai fxi-n3f3i --pj-p

The following three commands go to the control inputs of blocks 5-7, which convert the resulting value of frequency fxi to the physical dimension of the parameter using the calibration characteristic (1) of sensor 1-1: block 5 squares fxi and multiplies the result by A2, the value which is read from the output of block 9;

2

A5 - A2fxi2;

another multiplication unit 6 calculates the product of Aifxi; Block 7 summarizes the data received at its inputs, determines the final result, which is then rewritten to register 19-1:

Pl A2fxr + Aifxi + A0.

20

By filling the counter 15, a pulse signal is excited at its last output, which translates the counter 16 into the next position, and accordingly the switches 12 and 13 with memory blocks 8-11, preparing the device circuit for processing the information accumulated by the converter 2-2. At the same time, the trigger 17 with the switch 18 is returned to the initial state, if they were involved in the work, and the meter 15 itself is reset.

The second series of commands issued by the counter 15 is addressed to the control inputs of blocks 3-7 in the same sequence as the first, while blocks 3 and 4 calculate the frequency fX2, the remaining circuit elements convert it into volume flow rate Q according to equation (2 ). Derived value

flow is read into register 19-2.

The processing of measurement information generated by the third and subsequent frequency-code converters is performed using a similar algorithm,

moreover, in the nth channel, the values of the coefficients C2 and Co. considered from the outputs of blocks 9 and 11 are equal to zero and the final result is determined by the ratio

50

w fx

60

 rpm

By filling the counter with 1 b pulses, it is zeroed and the processing cycle of the measuring information is repeated.

Claims (2)

Claim 1. Device for measuring parameters of frequency sensors, comprising first and second pulse counters, as well as A clock pulse generator, characterized in that, in order to improve the accuracy of the device and expand its functionality, frequency sensors have been introduced to frequency-code converters by the number of frequency sensors, a block dividing unit, first to third number multiplier blocks, a number adder, the first and the second switches, trigger, registers by the number of measured parameters and the switch, the outputs of the frequency sensors are connected to the inputs of the respective converters, with the first information outputs of all the converters the frequency code is combined at the first inputs of the code division block, and their second information outputs are connected to the second inputs of this block, respectively, the outputs of which are connected to the first and second information inputs of the second and first information inputs of the third multiplication unit, outputs which are connected to the first and second information inputs of the adder of numbers, respectively, the outputs of the memory blocks are connected to the second information inputs of the first and third multipliers of numbers, with the third information inputs of the second multiplying unit numbers and third data inputs of the adder numbers, respectively, the output clock generator is coupled to the summing input of the first pulse counter, the first and second outputs which are connected via a switch to the information the input of the first switch and the control input of the code division block; the subsequent four outputs of this counter are connected respectively to the control inputs of the multiplier blocks and to the control input of the number adder; its seventh output is connected to the register entries and the overflow output from its zeroing input, with the first trigger input and with the summing input of the second pulse counter, the outputs of the first switch are connected to the read control inputs of the frequency-code converters, synchronizing the outputs of which are combined at the second input of the trigger, the output connected to the control input of the switch, the outputs of the adder of numbers are connected to the information inputs of the registers, the outputs of the second pulse counter are connected to the address inputs of switches and memory blocks, the overflow output of this counter is connected to its zeroing input, and register outputs are device outputs. 2. The device according to claim 1, characterized by the fact that each of the converters The frequency code contains a pulse shaper whose input is the converter input, a reference frequency generator, a switch, measured and reference frequency pulse counters, an additional pulse counter, two AND elements, two triggers, two registers, a block of coincidence elements, two memory blocks. , two delay elements and a switch, while the output of the pulse generator is connected to the summing input of the pulse counter of the measured frequency and the first input of the first element I, the second input of which is connected to the output of the second trigger, the output of this element And is connected to the first input of the first trigger and through the first delay element - to the inputs of the register entry, to the first input of the second element And and the input of the second delay element, the output of which is connected to the zeroing input the pulse counter of the measured frequency, to the initial setup input of the pulse counter of the reference frequency and to the first input of the second trigger, the outputs of the reference frequency generator through a serially connected switch and switch are connected to the summing input of the pulse counter of the reference frequency and to the subtracting input of the additional pulse counter, borrowing which is connected to with the input of the initial setup and with the second input of the first trigger, the output of the switch connected to the control input, the information outputs of the pulse counter of the measured frequency are connected to the first information outputs of the converter through the first register, the information outputs of the pulse counter of the reference frequency are connected to the first inputs of the element block matches and through the second register - with the second information outputs of the converter; the outputs of the first memory block are connected to the information inputs of the counters a pulse frequency reference and the additional pulse counter outputs a second block memory connected to the second inputs of the coincidence element unit output connected to the second input of the second flip-flop, and reading out the control the converter is connected to the read inputs of the registers and to the second input of the second element AND, the output of which is the synchronizing output of the converter. BUT. P FIG. 2 FIG. 3 Ј / Compiled by E.Solovyov Editor N.GorvatTechred M.Morgental Proofreader N.Revska Order 191 Circulation Subscription VNIIPI State Committee for Inventions and Discoveries under the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab ,, 4/5