SU1704224A1 - Device for discrete control of capacitor bank power - Google Patents

Abstract

The invention relates to electrical engineering and can be used to stepwise control the power of single-phase and three-phase capacitor batteries connected to four-wire networks. The purpose of the invention is to increase reliability. This is achieved by switching the capacitor battery 1 from linear to phase voltage or disconnecting it from the linear voltage by briefly turning on the semiconductor switch 5 at the time of the highest voltage on it controlled by the sync pulse driver 21, which ensures a quick decrease in the capacitor battery voltage to a level lower than the amplitude value of the phase voltage of the supply network. The logic circuit contains two zero-indicators 11 and 12, two control pulse shapers 9 and 10, two elements 13 and 17. three RS-flip-flops 7, 8 and 18, one-shot 22, an inverter, the element BAN 19. Delay element 15.3 Il. ate with

Description

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The invention of the k-to zl. Trztehn, 1-ke, and can be arbitrarily stepped control;;., aiUiSt -mat. wear t and one, XH: Oh, and, re, y; nii sc, i; - i:; i 4; pnux. under: s; H / - - ::: - .. xk h &gt.pox.ipOJOA-;;,.,.

 invented; - - increased reliability.

and FIG. 1 npcv ;;: Ki-3fl K3 functional scheme will build with IP ..-; yufig 2 diagrams nzgr xc ;; y and tpksz sigov c / c-isti; in fig. 3 - about; ome -: chys .. yy-nr-amma npprch; ::. log riche gn-1 part amplification.

Vs: s-ozsteo (Fig. 1} contains: -, opps-nsatornuyu battery 1, s / .n RUBC-D ks-jyuyu subkey keys neprodrodsk ..:; but to Klechada 2 for Gyudsoe / Mnon /. sdpsch, phase of the network, on another output of the chgr; from the first hk of the wire; oyy; key 3 - to K. j-mme A to connect the other phase of the mains supply in reverse order of the index interlacing 5 -:; Cleg-b for ldconnection of zero-mugo wire. In h before 7 and second 0 RS-trgg-eroa are connected to the outputs of the corresponding formers. 9 and 10 pulses yn pi ig; she and g-, whose outputs co-1 are united with control descents of the corresponding semi-php / mik keys 3 and 5. The null-indicators 11 and 12 are turned on according to the corresponding; oi (.p. semiconductor switches 3 "b. Psr u B code XI of element I13 is connected to 14 to connect the signal yn : .. voni Uf nz switching on the capacitor; -: ;; bstreei nz phase naprl- XOH .IG, rjTopjn skhodH2 - with in the output of the element 15control, that is. HZ - outputs of the null-indikatira 12. The input of the element 15 azdzrzhsh coe, c, iHO with s-g / odo; .-. inozrtor 16, the output of which is connected to the zero-indica-tsg with the CARE; -n 11 n the second pass x2 and 17. iopubii: input: 1 gleg. ntc And 17 is connected to the R-inputs of the G 5-trigger 6 and 13, with the lower RHEDOM of the membrane: a BAN 19 and 20 for connecting the control panel to the control panel; .ge Kond MsatoAis; Oatzrey 1 nonlinear neprlhg..e. The forwarding of the BANNER 19 sod ... N Zn unit with the generator of 21 sync pulses, turned on by terminal 4 for disconnecting the steep power supply network flooded and the collar 6 for connecting the zero state, the input of the BANE 19 element is connected to the S-input RS-flip-flop 18. This is why it is connected with 1 R-skhoi PZ-trmgorl 7 and the move .- "one-way;;: TOj: o4 22. The input one - IC-lsll 2 Ssedmnon with the output 1. RS-toiggoro 8. S-ehod which goody :; ; | with IJXP / .OM.: chTI 13, The output of elsmo-nta I1; 17 ssodin ::: with S-sxo-house, MirfC:; a 7,

The device works in accordance with the image; m

Let go: / u; MMti 2, I О are connected to the secondary channels A, C and the pulley of the channel /; C is pigg.; Corn corn corcoric iEJOHHO.

Pr. T pod1 ;. : on / to the signal of the control signal of the U1 at the condensate circuit (КЬ) 1 nz linear voltage (at terminal 14 c i i Log. O) and the moment of zero voltage on / | In the original key 3, the null indicator 11 is a pulse that translates the RS-flip-flop 7 with a stable signal with the Log signal. 1 at the output, which is supplied from the input of the formation of a pulse of 9 pulses, pida: o1 of what impulses to smoke t telles of the floor / pass of a new key 3, CB 1 Turns on on linapprp; -enu UAC. At the output, a null-indicator 11 is set. 1 (-t-:, r. Зк), the Former21 sync pulses forms at its output a sequence of: -, about F1 sync pulses (FIG, Ze) with MO ... CHTL- is reached. UAC voltages (Fg. Za) am: / .r. values.

To switch KB 1 from linear to phase voltage, the Log 50 signal is applied to terminal 50. 1 (moment 10, fig. 2). At the moment of the subsequent arrival of the sync pulse from the synch pulse generator 21 (time ti), the pulse appears on the output of the BAN element, which throws the RS flip-flop 1C into steady state with the Log signal. 1 at the output (Fig. 3a), which triggers the single-vibration device 22. Simultaneously, 5 it forms at its output a pulse (Fig. 3 and) sufficient to turn on the semiconductor switch 5. At the same time, the signal Log. 1 is fed to the R input of the RS flip-flop 7. which rerun. it to another steady state with the Log signal. O at the exit (Fig. ZJ). blocking the impulse control to control the switching on of the semi-progressive key 3. When one of the semi-internal valves is turned on; point 5, a short-circuit closed circuit is formed: phase C - one HO of the semi-primary valve of the main key 3 is one of the "semi-conductive" -.o key 5- zero prsnod. Moreover, at this time interval (ti-t2) - the frequency of the switched on valves on the upper 01st to / nights 3 and 5 will be the protrusion circuit. The nominal current I inp. (/ ig. 2) will have an inductive light guide and h .-- o-crg fast zopirai. h h CMCI.; - .. fnTO; bnogo poduodi (D.1 - .. Ch1.1LG. h1 I iVlil

popupro.yudpi opy l:;. h; 3 g - h. H1t j transition l current and ne; -. FIG. 2).

The voltage in kB 1 at this moment will be

U, c {t2) "UAo (t2bUco (t2) /

After locking the semiconductor key 3 at the output of the null indicator 11, a pulse Log appears. O (Fig. 3k), which are inverted by the inverter 16 (Fig. 3) and then fed to the delay element 15. The pulse of the delay element 15 (FIG. 3) is fed to the input X2 of the element 13. And then at the moment r3 the oscillatory process locks the semiconductor switch 5. The capacitor battery is disconnected from the network with a residual voltage lower than V2Um (Fig. 2).

At the time of the subsequent first equality of the residual voltage on the capacitor and the phase voltage UAO (moment m), a pulse appears at the output of the null indicator 12 (Fig. Ris), which is fed to the input of the XI element And 13. At the output of the element And 13 the signal appears Log. 1, which puts the RS-flip-flop 8 in a steady state with the Log signal. G at the exit (Fig. Zo). The pulse generator starts pulsing to turn on the valves of the semiconductor key 5. KB 1 is switched on without impact to the phase voltage UAO (time t4. Fig. 2).

If it is necessary only to disconnect the CB 1 from the linear voltage (up to the time t), the signal Log is set on both terminals 14 and 20. A. The operation of the circuit and the electromagnetic processes proceed as described above. At the time t4 of switching on KB 1, the phase voltage does not occur, since the control signal at terminal 14 is zero. KB 1 is under residual voltage, lower than V2 Itf, and is prepared for unaccented switching on both phase and line voltage.

Thus, the device provides a shock-free switching of the capacitor battery from one voltage level to another and its shock-free switching to any of the levels regardless of the previous mode of operation, as a result of which the reliability of the capacitor installation is increased.

Claims (1)

The invention The device for discrete power control of a capacitor battery containing two semiconductor switches, one output of a capacitor battery connected directly to a terminal for connecting one phase of the supply network, the other output through the first semiconductor switch to a terminal for connecting Another phase of the power supply network in reverse order of the index alternation and through the second semiconductor switch to the terminal for connecting the neutral conductor, the outputs of the first and second RS-flip-flops are connected to the inputs of the corresponding control pulse drivers, the outputs of which are connected to the control inputs of the corresponding semiconductor switches, the first input element and connected to the terminal for connecting the control signal to turn on the capacitor battery for phase voltage, the sync driver is connected between the terminal for connecting the other phase of the mains supply and the terminal for connecting the neutral wire, characterized in that it is equipped with a second element AND , the third RS trigger. two null indicators, an inverter, a one-shot, a delay element, and a BAN element, with the zero-indicators connected in parallel to the corresponding semiconductor switches, the inverse input of the BAN element, The R-inputs of the second and third RS-flip-flops are connected to a terminal for connecting a control signal to turn on a capacitor bank for linear voltage, the output of the BAN element is connected to the S input of the third RS flip-flop, the output of which is connected to the R input of the first RS - trigger and single-shot input, single-shot output is connected to the output of the second RS-flip-flop, the S-input of which is connected to the output of the first element And, the second input of the first element And is connected to the output of the delay element, and the third input - with the output of the second zero-indicator, output the first about the zero indicator - with the gathering of the inverter and the second the input of the second element And, the output of which is connected to the S-input of the first RS-flip-flop, the direct input of the element BANGE is connected to the output of the sync pulse generator, the output of the inverter is connected to the input of the delay element.