SU1697210A1 - Device for synchronization of system of control over valve converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in controlling thyristor compensators of reactive power, etc. The purpose of the invention is to improve the control accuracy and reliability of a valve converter by improving the symmetry of synchronization pulses. For this purpose, a synchronization voltage sensor 10 and phase-sensitive demodulators 7, 8, 9 are introduced, controlled by a binary counter 6 and forming compensation. The indicated voltage is summed with the voltage of the phase detector 1 in the adder 2 so that at the input of the low-frequency filter 3 there is a signal with a small ripple level. As a result, the controlled pulse generator 5 operates stably, and a symmetrical pulse sequence is formed at the outputs of binary counter 6. 3 h. the item of f-ly, 4 ill.

Description

ABOUT

yu VI

N

The invention relates to electrical engineering, in particular, to control systems for thyristor compensators of reactive power and other thyristor converters.

The aim of the invention is to improve the control accuracy and reliability of the gate converter by increasing the symmetry of the synchronization pulses.

On fmg. 1 is a block diagram of the device; in FIG. 2, schematic diagrams of the blocks; in fig. 3 is a diagram of a sync voltage sensor; In FIG. 4, a time diagram of the operation of the device.

The device (FIG. 1) consists of a phase detector 1 made, for example, in the form of a phase-sensitive demodulator, an adder 2, a low-pass filter 3 made, for example, in the form of an RC circuit, a PI controller 4, a controlled oscillator 5 , an eight-bit eight-meter counter, the first 7, the second 8, and the third 9 phase-sensitive demodulators, are made similar to the phase detector 1, the synchronization voltage sensor 10, and the output of the phase detector 1 and the outputs of the first 7, second 8, and third 9 phase demodulators are connected with appropriate the inputs of the adder 2, the output connected via serially connected low-frequency filter 3, PI controller 4 and controlled generator 5 to the counting input of a binary estimator b, whose outputs of the fifth, sixth and seventh bits are connected to the control inputs the third 9, the second 8, and the first 7 phase-sensitive demodules, respectively, and the eighth-bit output is connected to the control input of the phase detector 1, the signal input of the phase detector 1 is connected to the input of the synchronization voltage sensor 10, the output of which is connected to signal inputs of the first 7, second 8 and third 9 phase-sensitive demodulators.

The adder 2 and the low frequency filter 3 can be made in the form of a summing resistor-capacitive filter 11 (fmg. 2) and consists of four resistors 12, each of which connects the corresponding input and output of the summing filter 11, and a capacitor 13 connected between the output of the summing filter 11 and the common power point of the device. The PI controller 4 (FIG. 2) is made at the operational amplifier 14, the non-inverting input of which is input and the output of the PI controller 4, in series with the resistor 15 and the capacitor in the negative feedback circuit of the operational amplifier 14 and on a resistor 17 connected between the inverting input of the operational amplifier 14 and the common power point.

Managed generator 5 is made on

potentiometer 18 (trimmer) connected between the positive and negative poles of the power source (no polarity power source is shown). on six resistors 19-24, on the first 25 and second 26 transistors, the emitters of which are connected via the third 21 and fourth 22 resistors, respectively, to the negative pole of the power supply. and their bases are interconnected and connected via the second resistor 20 to the midpoint of potentiometer 18 and through the first resistor 19 to the input of the controlled generator 5 on a capacitor 27 connected between the collectors of the first 25 and second 26 transistors, on the first 28 and second 29 elements AND-NOT, the first input of the first element AND-NOT 28 is connected via the fifth resistor 23 to the collector of the first transistor 25, and the second input is connected to the output of the second element AND-NOT 29, and the first input of the second element AND-NOT 29 is connected to the output of the first element is NOT 28, and the second input is black The sixth resistor 24 with the collector of the second transistor 26, on the first diode 30, cathode connected to the collector of the first transistor 25. and the anode to the output of the first element EH E 28, on the second diode 31, cathode connected to

the collector of the second transistor 26, and the anode with the output of the second element AND-HE 29, the output of which is the output of the controlled generator 5.

In this case, the elements AND-NOT 28 and 29

connected by power between the additional pole and the common point of the power source. The sensor 10 synchronization voltage can be performed (Fig. 3) and in the form

element 32 of the sample-storage (chip), the signal input of which is the signal input of the sensor 10 synchronization voltage, the imager 33 on the front and the fall, the output of which is connected to

the control input of the sample-storage element 32, and the input with the control input of the synchronization voltage sensor 10 and inverter 33 (performed on an operational amplifier), whose input is connected to the output of the storage-storage element 32, s output is the output of a 1C sensor eg synchronization, and (Fig. 1, dashed lines), the signal input of the sensor 10 of the synchronization voltage is connected to the output of the phase detour-1, and the control input is connected to the output of the eighth digit X8 of the binary counter 6.

The device works as follows (time diagrams, Fig. 4).

The signal input of the phase detector 1 (Fig. 1) receives the synchronization voltage Uc (Fig. 4), and the control input – synchronization pulses Uxac output the eighth digit of the binary counter 6. A voltage is generated at the output of the phase detector 1 (at a signal 1 at the control input of the phase detector 1, the latter inverts the synchronization voltage, with the signal O, the phase detector operates as a voltage follower), which contains a variable component and a constant component, the control error. The magnitude and sign of this adjustment error depend on the phase difference between the indicated signals at the inputs of the phase detector 1.

The signal from the output of phase detector 1 (time diagram Ui) is fed to adder 2, where the main part of its variable component is compensated (the time diagram of the compensating component UK is shown by a dotted line). The resulting signal from the output of the adder (time diagram Da) is processed by a low-frequency filter 3, which eliminates interference and higher harmonics, and is fed to the input of the PI controller 4, which provides the appropriate control law. The control error filtered in this way acts through the PI controller 4 on the input of the controlled generator 5, controlling its generation frequency. The pulses from the output of the controlled generator 5 are fed to the counting input of binary counter 6, which operates in code 128- 64-32-16-8-4-2-1. As a result, at the outputs X1 ... X8 of the bits of the binary counter 6, sequences of rectangular synchronization pulses with a duty cycle of 2 are formed (for example, time diagrams Uxs, Uxe, Uxv and Uxs).

The frequency of the controlled oscillator 5 is adjusted so that the phase difference between the synchronization voltage Uc and the square synchronization pulses from the output of the eighth bit X8 of the binary counter 6 is equal to l / 2 (the regulation error is zero). This state of operation of the device is referred to as synchronization mode. Compensation of the variable component voltage. the output of the phase detector 1 is carried out in the adder 2 as follows. The synchronization voltage is supplied to the input of the synchronization voltage sensor 10, nor the output

which produces a signal equal to the amplitude value of the synchronization voltage (Uio time diagram). This signal (Uio) is converted by the first 7, second 8 and third 9 phase-sensitive demodulators into opposite-polar symmetric rectangular pulses (time diagrams U, Us and Ug). The first 7, the second 8, and the third 9 are phase sensitive

0 demodulators controlled by pulses

synchronization with the outputs of bits X7, X6 and

X5 respectively binary counter 6

(timing charts Ux, Uxe and UXB).

The gains of the first 7, second 8, and third 9 phase-sensitive demodulators are 0.7; 0.3 and 0.15. The resulting signal Utc Uy + Us + Ug in the form of voltage of phase-sensitive rectifiers 7, 8 and 9 is compensating

0 component (time diagram Uk, shown by a dotted line), which neutralizes the effect of the variable component from the output of the phase detector t in adder 2. Thus, filtering control error 5 already at the output of adder 2 low frequency filter high-frequency components of the signal, has a small time constant. In tracking mode

0 device sync voltage phase synchronization Uc (capture mode) the signal at the output of the filter 3 low frequency is almost absent, which is a condition for the stability of the generation of pulses controlled by the generator 5. The generation frequency with high accuracy is equal to 256 f network at any time interval. Consequently, the parameters of synchronization pulses at the outputs of binary meters 6 are also of high stability. This is especially important in control systems of tmristor converters, when, according to the algorithm of functioning, each time of the counter WELLS FOR a specific time.

In addition, the small time constant of the low-frequency filter 3 improves the tracking speed (adjustment) of the device for changing the phase or frequency

0 sync voltage. The number of phase-sensitive demodulators (7, 8, 9) can be increased to four or five. Then the filtering of the adjustment error in adder 2 is improved. However, a further5 increase in the number of demodulators operating at a higher frequency does not give a visible effect, since the arising disturbances in the control loop of the device become in magnitude and frequency comparable to the signals from these outputs.

additional phase-sensitive demodulators, adder 2 and low-frequency filter 3 can be in the form of a summing RC filter 11 (FIG. 2), which is easy to implement. The output of the summing filter 11 is in good agreement with the input of the non-inverting PI controller 4 (Fig. 2), which has a large input resistance. Its transfer function

W4 (P) (1 + TiP) / T2P,

where P is the Laplace operator;

Ti R15C16;

T2 R17C16:

R15 and R17 are the resistance values of the resistors 15 and 17;

C16 is the capacitance value of the capacitor 16.

Fig. 2 shows a schematic diagram of a controlled oscillator 5. The AND-HE elements 28 and 29 have an RS-trigger, which in operation is in one of two stable states: or when the output 1 of the first IS-28 element is 1 and, on the output of the second element, NAND, or, conversely, when at the output of the first element NAND 28 is O, and at the output of the second element NAND 29, 1, Signal 1, close to the positive voltage of the power source, served in the first case through the first diode 30 and in the case of the case through the diode 31 to the corresponding plate the capacitor 27, while the second capacitor plate remains at a potential that decreases as a result of capacitor 27 being recharged with a second current source (second transistor 26, fourth resistor 22) in the first case and first current source (first transistor 25, third resistor 21) - in the second case.

Since the plates of capacitor 27 are connected through protective resistors 23 m 24 to the RS-flip-flop installation inputs, when the potential on the said capacitor 27 plate drops to a zero trigger threshold, the latter is transferred, so that for the first case the outputs of the first AND-28 element 28 the signal O is set, and the output of the second element is NOT-HE 29 1, and for the second case, vice versa. The recharge rate of the capacitor 27 and, consequently, the frequency of the controlled oscillator 5 is controlled by the current sources (transistors 25, 26 and resistors 21, 22) by supplying the corresponding control voltage to the transistors 25 m 26 bases 26 from the output of the PI controller. torus 4. Simultaneously to the base

the transistors 25 and 26 are supplied from the output of the potentiometer 18 through the second resistor 20 to the bias voltage.

In the operating state of the device (in the capture mode), the potential at the output of potentiometer 18 is determined by the value such that at the output of the PI controller 4 the voltage is close to zero, which is necessary to provide a symmetric zone of action of the PI controller 4 on the output voltage. The ratio of resistors 19 and 20 determines the width of this coverage area.

Sync voltage sensor 10

5 (Fig. 3) works as follows. The voltage from the output of the phase detector 1 (timing diagram Ui) is fed to the signal input of the sample-storage element 32, which is controlled by the driver

0 33. On the front and decay of synchronization pulses from the eighth-bit output X8 (time diagram Uxs) of the counter 6, the driver 33 generates short control pulses (time diagram Ozz),

5 in time coinciding with the moments of the negative maxima of the voltage from the output of the phase detector 1, which are equal in magnitude to the amplitude value of the synchronization voltage Uc. At the exit

0 of the sample-storage element 32, a signal is generated equal to the amplitude of the synchronization voltage Uc of negative polarity, which is then inverted by the inverter 34. Thus, at the output of the sensor 10

5, the synchronization voltage is generated, a signal equal in magnitude to the amplitude of the synchronization voltage Uc (timing diagrams 1N and U34).

If it carries out the formation of its control pulses for the sample 32 storage element using a linear decoder connected by inputs to the outputs of binary counter 6, at times of positive maximum voltage Ui

5 from the output of the phase detector 1, using the corresponding output as the output decoder, then the specified signal, equal to the amplitude of the synchronization voltage Uc of positive polarity, can be directly generated without an inverter 34, i.e., a synchronization voltage sensor and a phase-sensitive sensor are inserted into the device - demodulators controlled by a binary counter, forming a compensation voltage, as well as an adder, in which the voltage of the phase detector and the compensation voltage are summed so that at the output of the adder and, respectively etstvenno, inlet filter The signal low frequency control has a small small level

pulsations. At the output of the low-frequency filter, the voltage ripples are practically absent. The controlled generator is stable. Consequently, pulse sequences with high temporal characteristics are formed at the outputs of the binary counter.

Claims (4)

The use of a synchronization device in a valve converter control system also ensures high symmetry of the control pulses. Claim 1. Device for synchronizing a converter converter control system comprising a phase detector, the signal input of which is used as a device synchronization voltage input, a low-pass filter connected in series, a controlled pulse generator and a binary counter, one of the outputs of which is connected to a control input phase detector, characterized in that, in order to improve the control accuracy and reliability of the valve converter by increasing the tracking accuracy on Synchronization, phase-sensitive demodulators, a synchronization voltage sensor, and an adder were introduced, the outputs of the binary counter were used as the outputs of device synchronization pulses, the control input of the phase detector was connected to the last output of the binary counter, the input of the synchronization voltage sensor was connected to the input of the phase detector, the output with the signal inputs of the phase-sensitive demodulators, the control inputs of which are connected to the corresponding ones, starting from the last but one output of the binary Meters withstand outputs - to one input of an adder, the other input of which is connected to the output of the phase detector, and an output - with an input filter Coy low frequency. 2. The device according to claim 1, characterized in that the adder and the low-frequency filter are designed as a summing low-frequency filter. 3. The device according to claim 1, characterized in that the output of the low-frequency filter is connected to the input of the controlled pulse generator through the additionally introduced PI controller. 4. The device according to claim 1, characterized in that the synchronization voltage sensor is made in the form of a sample and storage element, in which the signal input is connected to the output of the phase detector ' and the output is the output of the synchronization voltage sensor, and a control circuit wherein the output is connected to the control input of the sample and hold element, and the inputs are connected to the outputs of the binary counter.  - -h g 12 (2.5) 1 i / 4 Ј (ЈD- # 7  I -Un21 gb 20 sh Pg.2 thirty - J Ui U9 r-, f I- ,, 1t ". i "J Uxe R "g.Z. tit. art r- I  -V-v Uii U4 + UK J