SU1385266A1 - Oscillator - Google Patents

Abstract

The invention can be used for porting pulse generators with electronically controlled frequency. The invention expands the functionality of the generator by generating pulses with both a duty cycle close to zero and one, and a duty cycle of 0.5. The generator contains three transistors 6, 11 and 14, three comparators 1,4 and 18, resistors , capacitors, input and output buses. On bus 2, pulses with a duty cycle close to zero are formed, on bus 5 - with a duty cycle close to unity, and on tires 10 and 13 - pulses with a duty cycle of 0.5. On the bus 19, sawtooth pulses are formed with equal angles of inclination, increase and decrease. After the supply voltage is applied, the generator is set to a predetermined, previously known state. 2 Il. W S (L with OO 01 Ci O5 Thebes.

Description

The invention relates to a pulse technique and can be used in the construction of pulse generators with an electronically controlled frequency.

The aim of the invention is to enhance the functionality and the field of application by allowing pulses to be generated both with a duty cycle close to zero and close to one, and with a duty cycle of 0-, 5.

Fig. 1 is a schematic diagram of a generator; 2 shows time diagrams for his work,.,

The generator contains the first comparator 1, the non-inverting input of which is connected to the offset bus 2, the output through the integrator 3 to the non-inverting input of the second comparator 4, the inverting input of which is connected to the generation frequency control bus 5, the emitter of the first transistor 6 connected to the common bus the base is connected via the first resistor 7 to the output of the second comparator 4 and the first output bus 8, through the second resistor 9 to the second output bus 10, to the inverse of the first comparator 1 and to the collector of the second transistor 11, The mitter of which is connected to the power supply bus and via the third resistor (load resistor) 12 with the collector. The first transistor 6, with the third output bus 13 and with the emitter of the third transistor 14, whose collector through the fourth resistor 15 is connected to the base of the second transistor 11, and the base The fifth resistor 16 is connected to the fourth output bus 17 and the output of the third comparator 18, the inverting input of which is connected to the common bus, and the non-inverting input to the fifth output bus 19 and the integrator output 3.

The device works as follows.

Consider the operation of the generator from the point in time (see Fig 2) when the generator is energized by the generator power source. Wherein

the transistors 6, 11, and 14 are locked, the voltages on the ladders 8, 10, and 19 are zero, and the voltage on the output buses 13 and 17 is high. Integrator capacitor 3 is discharged, and the voltage across

0

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0 5 o

five

five

0

five

The output of integrator 3 is zero. Starting from the moment t (see Fig 2), the voltage from the output of the comparator 18 is high, because the positive voltage goes to its non-inverted myiPi input from the output of the integrator 3, the voltage from which gradually increases due to the output of the comparator 1 is supplied with a positive polarity voltage (the voltage at the non-inverting input is zero, and the busbar voltage is supplied with a positive polarity bias voltage).

Thus, when supplying voltage to the generator, the latter without resetting it to the initial state can be established only in a certain specified state,

After time t (see Fig 2), the indicated state of the generator remains unchanged until time t (see Fig 2) when the voltage from the output of the integrator 3 exceeds the voltage U gj on the bus 5 of the generator frequency control. At the output of the comparator 4. and the output bus 8, a high potential is formed, from which the transistor 6 is unlocked through the resistor 7, as a result of which the voltage on the collector of the transistor 6 decreases and the transistor 14 opens, as the voltage from the base of the transistor 14 from the output of the comparator 18 through the resistor 16 and the collector-emitter of the transistor. 6, and the collector current of the transistor 14 begins to flow and the base current of the transistor 11, the transistor 11 is saturated and its collector and output bus. 10 does not form a high potential, the voltage on the output bus 13 is close to zero due to the saturation of the transistor 6. At forming a voltage on the inverting input of the comparator 1 is more volatile; a negative potential is formed on the bus 2 at the output of the comparator 1, under the action of which the output voltage from the output of the integrator 3 begins to decrease. As soon as the voltage from the output of the integrator 3 becomes lower than the voltage on the bus 5, the voltage at the output of the comparator 4 becomes zero or negative, depending on the type of comparator 4 used, the voltage on the output bus 8 again becomes equal to zero. Pulse duration

bus 8 is determined by the speed of the elements used in it and the constant time of integrator 3 (the duration of the output pulse is equal to the time at which the voltage from the output of integrator 3 becomes less than the voltage of the comparator 4 to return to its initial state). After the comparator A returns to the initial state, the state of the transistor 6 remains unchanged, since it is saturated with the current of the resistor 9,

At time t (see Fig.2), the voltage from the output of the integrator 3 becomes less than the voltage at the inverting input of the comparator. The T8 and the voltage at its output become equal to zero, the transistors 6, 11 and 14 are locked, the voltage on the bus 10 becomes close to zero, and the voltage on the bus 13 becomes high (equal to the voltage of the power supply source E). The voltage from the output of the comparator, torus 1 becomes positive and the voltage from the output of the integrator 3 begins to increase, the comparator 1 returns to its original state and the voltage at its output again becomes high.

Further, the processors in the generator are similar to those considered.

With a change in the voltage value and. „On the bus 5, the access time changes

The operation level of the comparators 1, 4 and 18, as a result, the frequency of the generator also changes. The maximum frequency of the output pulses corresponds to the voltage on the bus 5, close to zero, which can be only a few microvolts, while the minimum frequency is determined by acceptable voltages. the voltage across the comparator is tens of volts, i.e., the pulse frequency control range is more than 3-6 orders of magnitude. The stability of the generator depends mainly on the stability of the integrator 3,

Thus, the proposed generator on bus 1 forms short

five

0

five

0

five

0

impulses with a duty cycle close to zero, on bus 4 — pulses with a duty cycle close to one; on tires 10 and 13 — pulses with a duty cycle of 0.5, but out of phase on bus 19, sawtooth pulses with equal inclination angles of increase and recession. The generator can have a powerful output at load 12 with a high efficiency, after the application of the supply voltage is established in a certain previously known state

Claims (1)

Shadow Formula A generator containing a generation frequency control bus, two comparators, an integrator whose input is connected to the output of the first comparator, and an output to a non-inverting input of the second comparator, the inverting input of which is connected to the generation frequency control bus, and output BUS that differs in In order to expand its functionality and application area, a third comparator, five resistors and three transistors, the emitter of the first of which is connected to the common bus, are additionally introduced into it, the base is connected via ne rvy resistor with the output of the second comparator and the first output bus, through the second resistor - with the second output bus, with the inverse input of the first comparator and with the collector of the second transistor, the emitter of which is connected to the power supply bus and through the third resistor - with the collector of the first transistor, from the third day off The third transistor is connected to the base of the second transistor, and the base through the fifth resistor is connected to the fourth output bus and to the output of the third comparator, the inverting input of which is connected to the common bus, and the noninverting input output 50 bus and integrator output. and 8Ш S t ,. iiSirixi FIG. 2