SU1690213A1 - Device for interpolation of tv picture signal - Google Patents

Abstract

The invention relates to television and can be used to reconstruct television images (TIs) in scalers. The purpose of the invention is to improve the quality of the television signal by increasing the steepness of the signals of brightness differences. The device for interpolating TI signals contains an input storage unit 1, registers 2, 5, 8, 6, 7, buffer operational storage units 3, 4, block 9 linear interpolation, multiplexers 10, 14, delay blocks 15, 11, 12, correction block 13, control block 16. By introducing correction block 13 during scaling, it became possible to reduce blurring of the boundaries between image areas of different brightness. This is achieved by attracting the value of the interpolated point to the value of the nearby point from the sample with different weights. However, image splitting into separate elements does not occur, since the coefficient of attraction depends on the distance to the interpolated point from the sample points. 6 silt, (L with Os Yu O yu

Description

Isolation uiHnc-ii i i s i mz. And Bcds z h may Ofctt i l) i n, o /, ECC of the station is known for touch, and - NJ j, c s s devices) magst it and irei.,

The purpose of the invention of ynv4Uisi was to increase the steepness of the signals by dropping

Nz FIG. 1 predp / cffig electrical circuit POSFOLIETE ingressively susceptible signals –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– block .., and h COHI - r i rug / gur on electric L / em alo C li) interpolation, in fig 5 - turkal ryle to the three block diagram. to rekitsich nafi (6 - structural electrical sowing, control unit.

The device is a TIMAN C TIM of the image of the image (1) which contains the input BLU 1, the first register 2, the new 3 m of the second 4 bu ern ones are more efficient than the last, block 5, the fourth and fifth fifth of the h

8 rsg LSTRY, block 9 GSHNZ N} "IN RIOLATI / 1,

the first multiplexer, the fourth one, and the RS tmi, 12 blocks zad8r s (m, 5 s) 3 erresd, which multiplexer is; By the first unit, s delay and block 16 ulrzzi nor

Device work with s rt8fivtci JMP sera oom

Iphroi eneflikiich - i (, os raei ca enter the south of the zsso hs iyuyushchy block i On the qH5r pr / zoeoi and displaying the south of w3o5p vei in the usual ziomtomkayu eat 1 z tyi it IU yo goto 17 20, d dots 21 2С tii- -, -sleep. Deny; tourism B one; bsa ka id 3, S composition vcho / lpag. 5sl I I enter 2 and 25 gam-m l sor 26 V schemes 24l -11 pap to a naaei iHn is depicted at the center of the sanwpjpae 1 center, which is determined by the OCHDRZTZ signal to be sent to the blocker; in / “Itch ° Zagss implement 1 poeter created (, and the time when the next cadre mrojez; chen / ii es / t and go to one of the 2 m circuits m 2C patch, then on a different PEMRTC information scheme, the SCER s are most likely to be mucked by a pexor 26 ip or buffer block 3. A memory from the i1 m 25 memory, nir 3 (.ri / sampling of cmfroz-fs (in the case of the signal, the signal coming to the jp j year, mark by 7fl, n, the mark will increase / menir mch masi.tab nravigo1 g |

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“I u bloi of 16 g of the reserve” Sample of banners on “successively recorded buffer or 3 on time Tst, equal to a1;, oh hour d.1 ,, pottii leneBwsHOdnogo I1ob g, oii f,., D 52 uc) But FIG. H is given if irMetb ex. 5; an aforementioned valid / (very large scale factor) TZNIR M 1 In i-circuit 24 and 25 nd (ir, iM is recorded then I tw 17-20, and

t-POINTS 2-7 i aL iHCji;, fOfCP B 9 1-UY

in) parapol i4 i and block 13, i 4 First le rc fe.vi11 24 Look for 2 s of the buffer tree 3 L p p / iOAOfi Kc Mx Tg read 17/1 18 by one cfoOKM Thereafter, i leaked i-many television lines , the number of which is determined by the coefficient MO of the shgabiroza-and / t is the value of M — counts | VS ”on the circuit, 24 or 2 memories does not occur during the M-th display. from the CI files of the foL6K value c / icqyrouie1 (t1 and 19 and 9P) j Scored Chg e "and S1P1, it was taken in a buffer 5fold Chdroir 1a neraz reschstr peck value. 17 and 13 of the previous line of record 7; in, spiib iT; block 4, hous buffer connection with regigmro 6, & r-t, goov 5 and 6 pidglyeny vksdЈ | i h & j, TO-J / h with S RSZ / Gb aie etogs psi rosled vs elslsg sm / chchan and from the berber U olikigz s / i 4 s Dwi he gk 5-3 h. f, SHd and P lO iff 1 // and C1.tae | Stvschosch 13 W-a-en1 hh Ґ0 O), (0, i Hnn) or {1} h m 1m-a / 1le; zi & i koatsra and nitrotetot & yy & c. r and, obrz Gn-a1 (p h jhe with i u n cr1 (|, s 6-8 & 1 And TjlO / ° Pi1 P | C i m pri g YATSII

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, oche: with Tr1, pf account for “ee” 2 i e FIG. 2, in the block § i | .ntog, about / 1 pii oksx orDf- ic y / z reapy r to i a i t f o t f b e c h f f o matrices 1 rcoTB6T (irj n p 2 e I a a-iT, 2}

j Bragtch i pho psi ps solutions, gcht; turghe sgdega goy and M f gpo Q h HI dt knowledgeable and Af. i) in r. Vinc with coop / eoy gpucher- -ID r / t а / 1-е i 1нrepi Ол ц i

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I, j - coordinates of the calculated point relative to the selected basis, given by the points A (0,0), A (0, n), A (n, 0), A (n, n);

n - the scale of the interpolated area (p M) .5

When calculating A (, j) by formula (1), a uniform change in the luminance values A (l, j) is achieved within each of the interpolated squares. For real images, such a uniform variation does not agree well with a mathematical model of images, a characteristic feature of which is a sharp change in brightness at the boundary of areas with approximately uniform brightness. In order to increase the steepness of the change in the brightness of the points at the boundaries of different brightness regions, 15 and, therefore, to bring the resulting image closer to a real mathematical model, 20 correction unit 13 was introduced into the invention, the A (I, J) values coming from the block output. linear interpolation. The function performed by the correction unit 13 is defined by the following expression: 25 A (U) K (l, j) A (lJ) -A (x) + A (x), (2)

Where

A (0, 0), if l / 2, J n / 2; A (0, n / 2, jn / 2; A (x) A (n, 0) if I n / 2, jn / 2; A (n, n) if I n / 2, J n / 2 ;

A (i, j) is the luminance value obtained as a result of calculations using formula (1);

K (i, J) are weighting factors depending on the distance between the interpolated point A (l, j) and point A (x).

The second inputs of the correction unit 13 receive the value A (x) from registers 5-7 or 8. The selection of the required value A (x) from the four values recorded in registers 5-8 is made by multiplexer 10 in accordance with the state (3) and under the influence of control signals fed to multiplexer 10 from control unit 16. The value of A1 (i, j) calculated in block 13 in accordance with formula (2) is output to the device through a multiplexer 14. Due to the fact that, according to formulas (1) - {3), it is not always necessary to calculate the values for interpolation A1 (,), the values of A (l, j) from block 9 of linear interpolation and the values of A (0,0), A (0, p), A (n, 0), A (n, n) from registers 5-8. In order to correct the delays that occur during end-of-phase calculations & in block 9, linear interpolation and correction block 13, blocks 11 5 are entered into the device.

10 15 20 25

thirty

35

40 45 50 55 15 delays. These blocks are sequentially connected registers, in which information is delayed, -: and the same number of ticks for calculating the values of A (l.j) and A (l.j) in block 9 of linear interpolation and block 13 of correction,

The linear interpolation unit 9 (Fig. 4) performs the calculations A (l, j) according to the formula (1) and includes 27-24 multiplication circuits, pipeline registers 35-41 and adders 42-44, wherein cve -Multipliers can be implemented on the basis of high-speed permanent memory devices (ROM) with a sampling time of T 100 not. The inputs of circuits 27-34 multiply the values A (0,0), A (0, n), A (n, 0), A (n, n) from registers 5-8 and the values of / n, j / n, (), (1-j / n) from control block 16. In multiplication circuits 27-34 and adders 42-44, the value of A (i, j) is calculated, and pipeline registers 35-41 are necessary for real-time linear interpolation unit 9 to work in real-time with a data acquisition period equal to signal td. Therefore, the timing of the coke-al-type registers 35-41 is carried out by the SI signal coming from the control unit 16 and having a period equal to TD.

Correction unit 13 (Fig. 5) performs the calculation of the value of A (i, J) according to formula (2) and includes adders 45-47, pipeline registers 48-53 v multiplexer 54. The inputs of the correction unit 13 receive the value A (t, J) from block 9 linear interpolation and the value A (x) from the output of multiplexer 10 through block 11 delay. The adder 45 performs the function A (i, j) + A (x), but due to the fact that the lower order bit is not supplied to the register 49 from the outputs of the adder 45, the value of 0.5 A (i, j) is generated at the output of the register 49 + A (x). Similarly, adders 46 and 47 are turned on. As a result, functions 0.75 A (i, j) + 0.25A (x), respectively, are formed at the outputs of registers 51-53; 0.5A (i, j) + 0.5A (x); 0.25a (i, j) + + 0.75A (x). These functions correspond to formula (2) with selected weighting factors K (i, j).

The weight coefficients K (i, j) are chosen based on two conditions; as far as possible, maximize the gradient of the difference; Prevent image decay into separate fragments.

Conveyor registers 48-53 provide the ability of the block 13 correction in real time. To do this, they are clocked by the SI signal, equal to H nepl-JD1. VHI feM; SC P TaKH :: ili; .cr: -i; i; i of the signal Jg and prcdsl of l okgs. &Amp; control, multiplexer, f; -4 required value; A (, j): -: From the output of the bzhzhv 13 corrections, the switch "in ulp: e ;; eora 54 is carried out under the control of the signals coming from the control blocks 16, the control block 18 (FIG. two functional); nodes; - node "; read / write control for the 24 t circuits of the 2EJ memory of the firmware control node, for controlling aapmeyo, there are 24 point counters 55 and 5 rows in the 24 msh 25 memory circuit and the control unit 16 (3, flip-flop 57, OR 53, ROM 59 recording the h; element 60 at the output. The recording node is controlled by the SI sampling signals arriving at the counting counter of 55 points. by extinguishing impulse lines arriving at the counting input of the counter 56 lines m reset input of the counter 55 points, extinguishing impulses of the first and second fields arriving at the installation and resetting switches of the trigger 57 v INPUT of the OR 58 element. Counters of points 55 and lines 56 and the trigger 57 forms the address of the selected element, the write ROM 59, and in accordance with the Coordinate Center code. coming to the address entry :: ROM 59 we borrow, forms the permission form for recording in the schemes 24 and 25 pan-ti. This form permits the passage of recording signals through the logical element U 60. The address of the recorded discrete signal, which is produced by the recording signals, arrives at the Sema 24 and 25 memory through multiplexers 81 m 62, When reading information from the 24 l 25 address schemes on & the blocks also come in via multiplexers 51 and 62, but the address forma-phosphorus occurs in point counters 83 and system 64, the read start address is received by the rS counter 63 points from the ROM 65, and the HS counter 64 lines from the ROM 66. The initial read address is determined the value of the scale code coming on a The cable inputs are 113V 65 m 65. To switch on multiplexers 61 and 52, a signal is used from the output of flip-flop 67, which separates even and odd frames. This "e signal from the output of the trigger 67 is fed to the multiplexer 26 (Fig. 3). To control the counters: - streams 63 t- lines 64 use control signals coming from a firmware control node, which includes a firmware ROM 68 with data points (39 and lines 70 at the address run, and with a conveyor register 71 at the output, There is also an address counter 72. The address inputs of the firmware 88 of the microprograms, except for data from the zykhodoo schztchikoa 68 and sgoszh 7 (X will be sent to

% MiG.Ggb and Priyyak Pyrvog / torogo fields S yih-iDy Trstvry b L /, NachshN Kai VCT3- -ozka and zero-bvoe from the table, and 69 gchzk is carried out at the beginning of each line with a pulse of lines and then the reset signal, coming from the conveyor register 71. At the counting input of the counter 69, the signals are sampled by the SI, and reset occurs every M points, where Y is equal to the display image. The initial output of the counter of 70 rows is carried out by damping creeping pulses at the beginning of each fell or, by default, the signal “resetting the arrival of the conveyor register 71”. The counting input of the counter is 70 lines of damping pulses of lines, and the reset occurs every M lines to progressive sweep. The through sweep is taken into account by the sign of the first / second floor, coming from the output of the flip-flop 57 to the address entries of the firmware ROM 68. For each scale, the firmware ROM 68 forms consecutive sequential commands within two cs-words: at the right of the cycle, determined by the counter operation of 69 points, and the external loop, determined by the operation of the counter / 0 lines, Macro ROM 68, the microprogram of the microprogram the pipeline register 71 comes from the blocks of the device and contains the following control signals;

-signal sample of the next point. This signal is fed to the counting input of the counter 63 points, the change address of the readable value of 51 kz of 24 y, 25 memory circuits, n & resetting the 69-point counter to start a new cycle and to register 2, in which the data received from the 24 m 25 memory circuits are recorded; The signal follow-up period is equal to the scaling of the sampling period;

-signal sample of the next line. This signal is fed to the counting input of a counter of 64 lines, to the reset input of a counter of 70 lines and to the input of the loading of a counter of 63 points. The signal follow-up period is equal to the product of the following quench period — U-LU, pulses of lines ka scale;

- control signals for buffer blocks - 0x blocks 3 and 4; This field is used for the WBBLOCK signal: signal / f control of the address counter 72, which forms the address dp of the buffer blocks of 3 m 4. initial setting of the counter 72 of address 5 carried out by extinguishing pulses mm lines arriving at the reset input; forg

s

The start / read signal n-load signal n-formation from buffer blocks 3 and 4, these signals are formed in each M-th line (where CH is ..LfTs6) c. period, different produced / w of the sampling period and on the scale:

-signal zsgs informational and% register 5-8, this signal forshfUspsp. each line with a period equal to the product of the sampling period by the scale;

- the switching signal of the multiplexer 10. The values of the strings of the dots vary within the squares bounded by the values 17-20 (Fig. 2);

- the switching signal of the multiplexer 14. Through the output multiplexer 14, either the output of the flea S or linear interpolation, or the output of the correction block 13, or c. the output of the multiplexer 10. From the output of the multiplexer 10, information arrives when the address of the displayed point corresponds to one of the values 17-19 or 20 (Fig.

2) and no additional computation is required. From the output of block 9 of linear interpolation, the information comes in the case, when the address of the displayed element corresponds to one for the weights (,), i.e. K (IJ) 1:

- switching signals of the output multiplexer 54 of the correction unit 13. The multiplexer 54 is switched by E COOTBSTCT & AV (AND ZYBRROM

the required weighting factor K (i, j) for each displayed element;

-codes of values l / n, j / n,. (1-i / n), (1-j / n), These codes go to circuits 27-34 mind-knife, or block 3 of linear-interpolation (FIG. four). The last signal that comes from the control block is the SI synchronization signal. This signal is transformed from the inputs of the device and goes to the linear interpolation block 9, the correction block 13 and the delay blocks 11, 12 and 15.

Thus, due to the introduction of the correction unit 13 when scaling, it became possible to reduce the blurring of the boundaries between image areas. nor having a different brightness. This is achieved by attracting, with different weights, the value of the interpolated point and the value of the nearby point. and, from the sample. However, the image does not disintegrate into separate elements, since the coefficient of attraction depends on the distance to the interpolated point from the sample points.

Claims (2)

DETAILED DESCRIPTION OF THE INVENTION A device for interpolating television image signals comprising an input storage unit whose input is the input of the device, and the information output is connected to an informational, us .-- rda. -..-; ns.psarc (., Oloklinen: :: - K; n interpolation, first n and agora buf .. onepi BHtifi zapomich -..- ..-, :: block,  And LLP is a NLT LPO -; SOL: m 0 /; 0 P-L i - i: f5: -iil, O T y L Ch. , 0 u with t:; . .-.;, THAT, WITH  yr; uch. the quality of tale m / yunnogo, by increasing. t; ::; we are ling- ;;;:; - .. gray drops, introduced the second, third, fourth v. Fifth registers, first 2.M.7 :. the second and third delay blocks and the corruption unit, the information one-first register is connected kmnfor-: l;: - n; the onsmu input to the first buffer .. c; -T ;; - 3TvieNoro of memory syok, many-. -g-tional output of which is connected to: -n-: FS: 1:) matsmszhny input of the second register, i-rri-vop, the output output of which is connected by j-je: -; (. information inputs of the second operational memory bl: g - tgvtego register, - pen m “nfor-my -; - u): -: Shi vi to the inputs of the block ;; in h r rkterP0:. g-cg .., pprzogo MULTIPLIKSRE. Btory infosm. the on-line block input of the linear inter: o;: G C to is connected to the second informational, 1- to the input of the first multiplexer, from inforkai. On the other hand, registers with information output of the fourth register, whose information input POA LCh W): -: K / NsOrMTSNNNYU OUT of the second operational buffer memory I remember.; -: -: OLOKZ, INFORMATION / 1. L STEPS OF THE FIFTH vO:.: Ci; jS HUDKLUCHVN K TRVT, IMFORZZIOS; - ;; :: ::;; : -: ogk bg, ok & ntcrpol - i; i.iy,: r; epi3oro multiplexer;, fourth; .-;:; l ;; p: .-: c; /; Onnom inputs to the r.gr ,, g-dodkgyyuche .- to 1: -; to the third register of the iifcixoflv, informational si -,: the course of the unit of the me- tery interpolation is connected to the multiforme input of the first delay unit: to the first informational input. O / -O ::: E correction, the information output of the first multiplexer is connected to the information input of the second delay block, the information output of which is connected to the second information input of the correction block and to the information delay number EXOP U of the third delay block, and g : and the ion outputs of the first delay unit, the correction unit and the third szero block are connected respectively to the first, second and third information input of the second multiplexer, the output of which is the output of the device, the second, third, fourth, fifth and sixth "control unit moves are respectively the inputs for the extinguishing pulses of the first field, the extinguishing impulses of the second zero, the extinguishing impulses of the strings, the synchronizing signals, the command code, the Scales of the code. Coordinate teams the center, the control and the address inputs of the input storage unit are connected respectively to the first control and the first address outputs of the control unit, the second address output of which is connected to the address inputs of the first and second buffer operational storage blocks, the data output of the control unit is connected to the data input the linear interpolation unit, the second, third, fourth, fifth, sixth, seventh, eighth and ninth control outputs of the control unit are connected respectively to the control input of the second register, to the control input of the first operational storage unit, to the control input of the second operational storage unit, to the control inputs of the second, third, fourth and fifth registers, to the control input of the first multiplexer, to the control inputs of the unit linear-interpolation, the first, second and third delay blocks and the correction block, to the additional control input of the correction block and to the control input of the second multiplexer. 17 21 X " one nineteen X “© o 20 22 o X №9 Fsch9. 17W X x 2 18 17 X 99 W x 17 X