SU1683174A1 - Time-to-voltage converter - Google Patents

Abstract

The invention relates to a measurement technique and can be used in digital devices for special and universal purposes. The purpose of the invention is to increase speed. The device contains two integrators, a source of model currents, a comparator, a sign analyzer, a pulse generator, and key and logic elements. High performance is achieved by obtaining information about the input signal during each clock frequency period. 2 Il.

Description

The invention relates to electrical measuring equipment and can be used in digital devices for special and universal purposes.

The purpose of the invention is to increase speed.

Figure 1 shows the functional diagram of the Converter; figure 2 - timing charts of his work.

The voltage-to-voltage converter contains the output bus 1, the first integrator 2, the first switch key 3, the switch 4, the source 5 model currents, the input bus 6, the second integrator 7, the comparator 8, the analyzer 9 characters, the common bus 10, the first D- trigger 11, generator 12 pulses, T-trigger 13, the first element And 14, the first and second blocks 15 and 16 of the reset, the second key 17 of the switch, the second and third D-triggers 18 and 19, the element NOT 20, the element 2I-OR- NOT 21, element NOT 22, second element AND 23, element OR 24,

In figure 2: 25 - the output signal of the generator 12 pulses, 26-signal on the input bus b, 27 and 28 - the output signals of the first and second integrators 2 and 7, respectively, 29 - the output signal of the comparator 8, 30 - the output signal of the analyzer sign , 31 - signal at the direct output of the first D-flip-flop 11, 32 - output signal of the element 2И-ИРИ-НЕ 21, 33 - signal at the direct output of the T-trigger 13, 34 and 35 - input signals of the first and second blocks 15 and 16 reset, respectively, 36 and 37 - the output signals of the first and second elements And 14 and 23, respectively, 38 - the signal at the terminal output w ya I.

The converter works in the following way:

Let the voltage Ux (t) Ux const 0 be applied to the input bus, then the output current of switch 4 will be an exemplary current of 10 O (i.e. - lo). At time to (figure 2) with the arrival of a pulse from the generator 12 pulse 00

s

i ui y. i s-.i poi D-trmgger 18, otilu- i: (., U.ICH and SL 15 stuffing, and T-trigger 13, “m MI i and) s jnnne Oh, allowing the pro jiir the second element And i zh | ipr needles through the first element AND 14. ten he D DIpnrrepa 19 remains t w-num, i.e. the single input level of the second epement And 23 opens the second key 17, with which the second input of the second the integrator 7 is supplied with a model current io. As a result of the above processes, the output eg the first integrator 2 changes from sl / l according to the law

Un

W

at

gpe T1 is the constant of the time of the first integrator 2, and that of the second integrator 7 is from 1alch | X conditions caused

nretmtsushchm tzktoi (1Bo - -T, where i «-2

the constant time piopoi of the integrator 7, 1 is the pulse of pulse following from the generator of 12 pulses) according to the law

m - U

1) 21 b h

 with Ra resistance of the second integrator

T f / R2 lodr.

i

Mo, “ng of time and (fig. 2) the output -equalities of the first and second integratoses 2 and 7 are equal to each other, which leads to the mooing of ICT 8. Signal s pslep; L / e. d 7li- nI ng 21, then the br-ci is a gch approach, p-toigger 19 p cc- with p i ho s ci t yu f l (| l x: include then (; ggo b155 15oos chepol On the other hand, the marketing team is i / iein yl Jf $ t P t (it’s the 17 Å key of the result of one or more of the world (O hi-) it’s 7 stanovigs equal to zero, from the first of all, it goes on, io, io, ear to the law.

G. South, it L 2) comes, from the generator 12 g / 1 mg / hour G neoj fbTaT 1 is based on the third D trigger 19 off t--, the second reset unit 16, and T-I perehotsigig e sigotney 1, the laying of it through the first Olsman I 14 and a decree through the second I and 23 The state of the second 0-grigger 18 HP | Zetz former, ha zero At the same time, the И level of the first slot And 14: t, Fyzaet the first key 3, with the help of Koyu-Sogo nor the first RCS first. Integrator 2 is supplied exemplary). As a result, the single voltage of the second integrator is a simulated with a from zero according to the law

J

ai

di,

and of the first integrator 2 - from the national conditions stipulated by the previous Uzi tact, with te () according to the law

Uiz - T + / Rilodt,

where Ri is the resistance of the first integrator 2

At the time point xs (Fig. 2), the comparator 8 is triggered, which causes the second D-flip-flop 18 to switch to 1 and, therefore, to the first reset unit 15 and through the first element 14 to the first key 3 open. As a result, the output voltage first integrator

5 2 becomes equal to zero, and the second integrator 7 continues to vary according to the same law.

As a result of these processes

tjС, t,

0 Ux dt- (and, P.IJrft-i U, dt Oh,

Lrl (.С7 1

 about -2t2

Bf-sЈs

k j U, cH- 0 Z l

b Hence, denoting t2-t0 T,

  Txt, t5 - accepting D - -f and Ri R2 R get UyT- (Ux-Rlo) TX1 - -UxTx1 0,

0UxT - (Uxlo) TX2 - “- Ux TX2 0

CH L I

tUxT UXT

Gx1 RTTlTx2 Rir

cfijjM is the sign of the input signal by hpHj / ep, and the time point te (figure 2) the output voltages of the first and second integrators 2 and 7 increase the output voltage of the first integrator 2 in this case at time t (figure 2 ) reaches zero, which triggers the analyzer 9 characters, which is set to the 0 + trigger level. With the arrival of the nearest pulse from the pulse generator 12, the first D-flip-flop 11 switches, and consequently, the switch 4, which is connected to through the first and second keys 3 and 17 positive power current to the inputs of the first and

g of the second integrator 2 and 7 Next, the work occurs as above.

Thus, in accordance with the principle of operation of the converter, the information about the input signal in the form

Claims (1)

g of the time interval Txj or TX2, which are identical to each other, is obtained in each period of the pulse sequence of the generator of 12 pulses. A voltage to time converter containing the first integrator, the first input of which is connected via a switch to the output of the switch, the information inputs of which are connected to the corresponding outputs of the source of exemplary currents, the second input is an input bus, and through the second integrator connected to the first input of the comparator and the output is connected to the second input of the comparator and the first input of the sign analyzer, the second input of which is the common bus, and the output is connected to the D input of the first D-flip-flop, the direct output of which is This is connected to the control input of the switch, and the C input to the output of the pulse generator and combined with the input of the T-flip-flop, the direct output of which is connected to the first input of the first And element, the output of which is connected to the first control input of the switch and a second reset unit, the outputs of which are connected to the third and second inputs of the first and second integrators, respectively, characterized in that, in order to increase speed, elements of NOT, 2I-ORIN, OR, the second element I, and the second and third D are entered into it triggers with R-inputs combined with and connected to the output of the pulse generator, the C-inputs of the third D-flip-flop directly, and the second D-flip-flop through the first element are NOT connected to the output of the 2I-OR-NOT element, the first inputs of the first and second groups of inputs are connected respectively to the right and the inverse outputs of the first D-flip-flop, the second input of the first group directly, and the second input of the second group through the second element are NOT connected to the output of the comparator, the D-inputs of the second and third D-flip-flops are connected respectively to the direct and inverse outputs of the T-trigger The key, the direct outputs of the second and third D-flip-flops are connected to the inputs of the first and second reset blocks, respectively, and the inverse outputs are connected respectively to the second input of the first element And to the first input of the second element And, the second input of which is connected to the D-input of the third D -trigger, and the output with the second control input of the switch and with the first input of the OR element, the second input of which is connected to the output of the first element AND, and the output is the output bus, while the auxiliary output of the switch is connected to the third input second integrator. fig-2