SU1677666A1 - Instrument to meter electrical capacitance and leak resistance - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be used in the construction of automatic digital meters. The aim of the invention is to improve the measurement accuracy and enhance the functionality by measuring the leakage resistance. The device contains an operational amplifier 1, resistors 2,5,7. terminals 3 and 4 for connection to the power supply, keys 6 and 10, terminals 8 and 9 for connecting the measured capacitance, four comparators 11,12,13 and 14, terminals 15,16,17

Description

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and 18 for connecting exemplary voltage sources, two triggers 19 and 20, a decoder 21, a pulse generator 22, a frequency divider 23, two elements 24 and 28, two counters 25 and 29, two registers 26 and 31,

a frequency multiplier 27 and a persistent storage device 30. High measurement accuracy is achieved due to the fact that the capacitance value is measured at almost zero current through the leakage resistance. 2 Il.

The invention relates to a measurement technique and can be used in the construction of automatic digital gauges.

The purpose of the invention is to improve the measurement accuracy and enhance the functionality by measuring leakage resistance.

Figure 1 shows the block diagram of the device; 2 shows timing diagrams for his work.

The device contains an integrator (operational amplifier) 1, the first resistor 2, terminals 3 and 4 for connecting the power source, the second resistor 5, the second switch 6, the third resistor 7, terminals 8 and 9 for connecting the measured capacitance, the first switch 10, four comparators 11-14, terminals 15-18 for connecting exemplary voltage sources, two flip-flops 19 and 20, decoder 21, pulse generator 22, frequency divider 23, element 24, first counter 25 pulses, first register 26. frequency multiplier 27, second element 28, second counter 29 pulses, permanently memorizing its device is 30 and the second register is 31.

The device works as follows.

Let the linearly falling output voltage of the integrator 1 U5 (to) immediately before the moment (Fig. 2), which triggers the comparator 14. In this case, the trigger 20 is set to O and the key b is opened. The voltage rise at the integrator output from the zero level to the Ui level begins. At this time, the element AND 24 is opened and the pulses from the pulse generator 22 arrive at the counting input of the counter 25, which is preset to zero. When the voltage at the output of the integrator 1 reaches the level Ui (time ti), the comparator 13 sets the trigger 19 in О

24 closes and the counting of pulses in the counter

25 stops, the key 10 is opened and the voltage at the integrator output begins to rise at high speed to the level of U2. At the moment of its achievement, the comparator 12 is triggered and the trigger 20 is set to one. By this time, the output of the multiplier 27 is set to a signal, the period of which is proportional to the number in the counter 25. At the same time, the key 10 opens and a relatively slow increase in voltage at the integrator output from the level U2 to level 11z begins (Fig. 2). At this time, the element E28 opens and the pulses from the output of frequency multiplier 27 begin to be counted by the counter 29. When the voltage on

0, the integrator output will become equal to Oz (time instant ta), the comparator 11 is triggered and sets the trigger 19 to one state, the AND element 28 is closed. A rapid voltage drop begins.

5 output of the integrator (section gz - ti). At the moment when the voltage at the integrator output with decreasing becomes equal to Ua, the output signal of the comparator 12 will transfer the numbers from the counters 25 and 29 to the registers 26 and

0 31, and the number transferred from the counter 29 to the register 31 will change in accordance with the record in the permanent storage device. Then, after reducing the voltage at the integrator output to zero cycle

5 is repeated.

Claims (1)

Claims An apparatus for measuring electrical capacitance and leakage resistance, comprising an integrator, terminals for 0 connect the measured capacitance, the first of which is connected to the integrator output, and the second to its input and through the first resistor is connected to the negative terminal of the power supply, the positive terminal of which is connected to the integrator's input through the first switch and the second switch and the third resistor with a positive power supply terminal, the integrator output is connected to the first input of the first comparator, the second input of which is connected to the first source of reference voltage, the output of the first comparator is connected to chnym input of a first trigger pulse generator, 5 the output of which is connected to the first input of the first element I, the output of which is connected to the counting input of the first pulse counter, the second input of the first element I connected to the first output of the decoder. 0 the second and third outputs of which are connected to the control inputs of the first and second keys, respectively, characterized in that, in order to improve the accuracy of measurement and enhancement of functionality, three comparators, a second trigger, two registers, a frequency divider, a frequency multiplier, are introduced into it, The permanent memory, the second element And and the second pulse counter, the counting input of which is connected to the output of the second element And, the first input of which is connected through the frequency multiplier to the output of the frequency divider, which is connected to the output of the pulse generator, the second input of the second element I is connected to the fourth output of the decoder, the installation input of the second pulse counter is connected to the gate inputs of the pulses of the first and second registers and the installation input of the first pulse counter, the outputs of which are connected to the corresponding information inputs of the first the register and with managers t, go the inputs of the frequency divider, the outputs of the second pulse counter through a permanent storage device connected to the corresponding information inputs the second register, with the first inputs of the second, third and fourth comparators connected to the output of the integrator, and the second inputs of the second and third comparators are connected respectively to the output the second and third sources of reference voltage, the second input of the fourth comparator is connected to the common bus, the output of the fourth comparator is connected to the installation input to the second trigger, the output of which is connected to the first input of the decoder, and the installation input to 1 is connected to the first output of the second comparator, the second the input of which is connected to the installation output of the first pulse counter, the output of the third comparator is connected to the installation input of the first trigger, the output of which is connected to the second input of the decoder.  t