SU1675805A1 - Device for diagnostics of valve converters - Google Patents

Abstract

The invention relates to a measuring and control technique and can be used to control valve converters, for example, used in railway transport. The purpose of the invention is to expand the field of application of the device by diagnosing valve transducers with simultaneous supply of pulses to the thyristors of the anodic and cathodic groups. The device contains elements OR 1,2, blocks 3,4 delays, counters 5, 6, formers 7. 8 pulses, trigger 9, elements AND 10,11, generators 12, 13 test signals, transformers 14, 15, 21,22, capacitors 16, 17, 19, 20, display unit 18, threshold amplifiers 23, 24, decryption unit 25, inputs 26, 31 of decryption unit 25, inputs 27, 28, 29, 30. Due to the introduction of counters 5, 6, drivers 7 , 8 pulses, trigger 9, the device provides diagnostics of valve converters operating with simultaneous feeding of anode and cathode groups to thyristors. 4 il. 16 CO with

Description

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The invention relates to a control and measuring technique and can be used to control valve converters used, for example, in railway transport.

The purpose of the invention is to expand the field of application of the device by diagnosing valve transducers with simultaneous supply of pulses to the thyristors of the anodic and cathodic groups.

FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of a decryption unit; in fig. 3 is a decoder circuit; in fig. 4 shows timing diagrams for the operation of the device.

The device (Fig. 1) contains the first 1 and second 2 OR elements, the first 3 and second 4 delay blocks, the first 5 and second 6 counters, the second 7 and first 8 pulse shapers, trigger 9, the first 10 and second 11 elements, and the first 12 and second 13 test signal generators, third 14 and fourth 15 transformers, third 16 and fourth 17 capacitors, display unit 18, first 19 and second 20 capacitors, first 21 and second 22 transformers, first 23 and second 24 threshold amplifiers, block 25 decoding, the fifth input 26 of the decoding unit 25, the first 27, the second 28, the third 29 and four 30 control inputs of the device, fourth input 31 of decryption unit 25. In addition, the power supply transformer 32, the thyristors 33 - 36 of the diagnosed gate converter and the load 37 of the diagnosed gate converter are also shown.

Block 25 decryption (Fig. 2) contains the formers 38 - 41 pulses, the decoders 42 - 45, the outputs 46 and 47, respectively, the formers 38 and 39 pulses. The decoder 42 (FIG. 3) contains pulse formers 48 and 49, respectively, at the back and front edges, And 50 and 51 elements, triggers 52 and 53, And 54 element, register 55, and outputs 56 and 57, respectively, of the pulse shapers 48 and 49. , outputs 58 and 59 of the trigger 52, outputs 60 and 61 of the trigger 53, outputs 62 - 64 of the register 55.

The first element OR 1 is connected to the first and second inputs, respectively, with the first 27 and second 28 inputs of the device, the output with the input of the first block 3 delays. The second element OR 2 is connected by the first and second inputs to the corresponding third 29 and fourth 30 inputs of the device, the output to the input of the second 4 delay block. The decryption unit 25, connected by an output to the input of the display unit 18, the first inputs with the corresponding first 27, second 28, third 29 and fourth 30 inputs of the device, the second input with

the output of the first threshold amplifier 23 connected by the first and second inputs, respectively, with the terminals of the secondary winding of the first transformer 21 connected by the first output of the primary

0 windings with a common bus device, with the first output of the primary winding of the second transformer, with the first conclusions of the secondary windings of the third 14 and fourth 15 transformers. The second conclusion is primary

5 the windings of the first transformer 21 are connected via the first capacitor 19c with a terminal for connecting the first terminal of the monitored valve converter, a terminal for connecting the second terminal

0 which is connected through the second capacitor 20 to the second output of the primary winding of the second transformer 22 connected by the leads of the secondary winding, respectively, to the first and second inputs of the second threshold amplifier 24 connected to the third input of the decryption unit 25. The first test signal generator 12 is connected by the outputs, respectively, to the terminals of the primary winding of the third transformer, which is connected to the second output of the secondary winding through a third capacitor 16c with a terminal for connecting the third output of the monitored valve converter

5 connecting the fourth terminal of which is connected via the fourth capacitor 17 to the second terminal of the secondary winding of the fourth transformer 15 connected by the first and second terminals of the primary

0 windings with the corresponding outputs of the second generator 13 test signals. The output of the first delay unit 3 is connected to the counting input of the first bis counter by the first input of the first element 10, connected by an output to the input of the first generator 12 test signals, a second input to the control input of the first counter 5, to the forward output of the trigger 9 and the fourth input 31 of decryption unit 25, connected by fifth input 26 with inverse output of trigger 9, to the first input of the second element 11, connected to the input of the second generator 13 test signals, the second input to the output of the second unit 4 delays and counters input of a second counter 6, a control input connected to inverted output flip-flop 9, and output via the first pulse generator 8 with the first input of the flip-flop 9, a second input coupled through a second pulse shaper 7 with the output of the first counter 5.

The device works as follows.

If the control pulses are received in pairs alternately at inputs 27 and 30 and then at inputs 28 and 29 of the device and at the same time at the control electrodes of the thyristors 33, 36 and 34, 35 of the thyristor bridge, the thyristors are first checked alternately, for example, anode ( thyristors 33 and 34), and then another - cathode (thyristors 35 and 36) groups of this bridge. The order of checking the groups is determined by the state of the signals at the outputs of the trigger 9. If the latter is in such an initial state that there is a Log at its direct output. 1, and on the inverse output of the log. 0. Thyristors of the anode group, i.e., thyristors 33 and 34, are first checked. If a pair of thyristor control pulses 33 and 36 from the device inputs 27 and 30 first arrived, then these pulses also appear at the outputs of the corresponding elements OR 1 and 2 and pass through blocks 3 and 4 delays. In this signal Log. O, coming from the inverse output of trigger 9, prohibits the passage of pulses from the output of block 4 delays through element 11, as well as the operation of counter 6. Signal Log, 1. coming from the direct output of trigger 9 to input of element I 10, allows passage to its the output of the delayed in block 3 at the time of switching the current to the thyristor 33 pulse. This pulse triggers the test signal generator 12, which forms a damped sinusoid with a frequency sufficient to eliminate the shunting effect of the load 37 and the power supply transformer 32.

With a good thyristor 33, the test signal passes through galvanic isolation, including transformer 14 and isolating capacitor 16, as well as thyristor 33, another galvanic isolator (isolating capacitor 19, transformer 21) and is fed to a threshold amplifier 23, which forms at output the square impulse that arrives at decryption unit 25. The appearance of a pulse at the output of the threshold amplifier 2.4 indicates a breakdown of the thyristor 34, and the absence of a pulse at the output of the threshold amplifier 23 indicates the break of the thyristor 33, i.e., the loss of its controllability.

On the falling edge of the pulse from the output of the delay unit 3, the counter 5 counts the pulses. At the moment of arrival of the second pulse from the output of the element OR 1, the signal is also sent to the thyristor 34, and on the falling edge of this pulse at the output

counter 5, a signal is generated that triggers the driver 7, which switches the trigger 9 so that a Log is established at its forward output. Oh, and on the inverse 5 output Log. 1. At the same time, the level of the signal from the direct output counter 5 is reset, and the element And 10 is blocked. The signal level from the inverted trigger output 9, counter 6 and element 11 is unlocked. Further

10, in a similar manner, test testing is performed alternately of the thyristors of the cathode group 35, 36.

The decryption unit 25 (FIG. 2) operates as follows.

5 The thyristor control pulses from the inputs 27-30 of the device are fed to the formers 39-41 pulses, the outputs of which form rectangular pulses with a duration from the leading edge

0 input pulse to the end of the half-period of the supply voltage. The decoding of the test result of each thyristor is performed by a separate decoder 42-45, whose structure is identical, (FIG. 3).

5The timing diagram of the decoding of the failure of the thyristor 33 of the Breakdown type, characterizing the operation of the decoders 42-45, is shown in FIG. 4. Triggers 52 and 53 are reset to the initial state of a pulse generated by shaper 49 on the leading edge of the signal from the direct output of trigger 9 before checking the anode group thyristors. At the same time, at output 59, trigger 52 is set to Log. Oh, on the course of 60 60 trigger 53 Log. 1. The decoding result is written to the output register 55 —from the trailing edge of the signal of the imager 48, which is triggered at the trailing edge of the signal from the direct output.

0 flip-flop 9. Shaper 48 generates a time delay that overlaps the arrival of a pulse from amplifier 23. As a result, decoder 42 detects the thyristor states: Open, Break, Good.

5 Thus, by introducing the counters 5 and 6, the formers 7 and 8 pulses, the trigger 9, the elements 10 and 11 and the new connections, the device can provide a sequence of checking the thyristors for

0 valve transducers with simultaneous supply of pulses to thyristors of the anodic and cathodic groups, which expands the field of application of the device.

Claims (1)

5 claims A device for diagnosing valve transducers, comprising a first OR element connected to the first and second inputs, respectively, to the first and second inputs of the device, the output to the input of the first delay unit, the second element OR. connected to the first and second inputs with the corresponding third and fourth inputs of the device, the output to the input of the second delay unit, the decryption unit connected to the input of the display unit, the first inputs to the corresponding first, second, third and fourth inputs of the device, the second input with the output of the first threshold amplifier, connected by the first and second inputs, respectively, with the secondary winding leads of the first transformer connected by the first output of the primary winding to the common bus of the device, with the first water of the primary winding of the second transformer, with the first terminals of the secondary windings of the third and fourth transformers, the second output of the primary winding of the first transformer is connected via a first capacitor to a terminal for connecting the first output of a controlled converter, the terminal for connecting the second output of which is connected via a second capacitor to the second - eye the primary output of the second transformer connected by the leads of the secondary winding, respectively, with the first and second inputs of the second n a horn amplifier connected by an output to a third input of a decryption unit; a first test signal generator connected by outputs to the primary windings of a third transformer connected by a second output of the secondary winding through a third capacitor to a terminal for connecting a third output of a monitored valve converter; a terminal for connecting a fourth the output of which is connected through the fourth capacitor to the second output of the secondary winding of the fourth transformer connected first m and the second conclusions of the primary winding with the corresponding outputs of the second test signal generator, characterized in that, in order to expand the field of application by diagnosing valve transducers with simultaneous pulses to the anodic and cathodic groups of thyristors, two elements are introduced into it, two counters , trigger, two pulse drivers, with the output of the first delay unit connected to the counting input of the first counter and to the first input of the first element I connected to the input of the first generation the torus of the test signals, the second input with the control input of the first counter, the direct output of the trigger and the fourth input of the decryption unit connected by the fifth input to the inverse output of the trigger, the first input of the second element And connected to the output of the second generator of test signals, the second input - with the output of the second delay unit and with the counting input of the second counter, connected by the control input with the inverse output of the trigger, and the output through the first pulse driver with the first input of the trigger, connected by V Ory input through the second pulse shaper with the output of the first counter.