SU1672554A1 - Operational amplifier - Google Patents

Abstract

This invention relates to amplifying devices. The purpose of the invention is to increase the common-mode input voltage range. An operational amplifier with differential input and output contains an input differential stage 1 containing a current generator 2, first and second P-channel transistors 3, 4, N-channel transistors 5, 6 of the first dynamic load, an additional input differential stage 7 containing the generator current 8, N-channel 9, 10 and P-channel transistors 11 and 12 of the second dynamic load, the second additional stage 13, containing the P-channel transistors 14 and 15, the first additional stage 16, containing N-channel transistors 17 and 18, amplify common mode voltage / USN / 19, containing current generators 20 and 21, third and fourth P-channel transistors 22 and 23, fifth and sixth P-channel transistors 24 and 25 of the first and second differential stages, respectively, additional N-channel transistor 26. Due to the effect of negative feedback on the common-mode output voltage, which is connected to the STS 19, a change in the output common-mode voltage that would have occurred without negative feedback on the output common-mode voltage will be suppressed. 1 il.

Description

The invention relates to amplifying devices and is intended for use in amplifiers for various purposes, which are elements of analog and analog-digital systems in the integrated version of field-effect transistors.

The purpose of the invention is to increase the common-mode input voltage range.

The drawing shows a circuit diagram of an operational amplifier.

The operational amplifier contains an input differential stage 1 containing a current generator 2, the first and

Secondary O-channels-1 ie transistors 3 and 4, n-channel transis. ,; s 5 and 6 of the first dynamic load, additional input differential cascade 7, containing 8 current generator, n-channel transistors 9 and 10, p-channel transistors 11 and 12 of the second dynamic load, second additional cascade 13, containing p-channel transistors 14 and 15, the first additional stage 16, containing p-channel transistors 17 and 18, common-mode voltage amplifier 19, containing current generators 20 and 21, third and fourth p-channel transistors 22 and 23, fifth and sixth p-channel transistors 24 and 25 first and second differents cial Caso VJ st ate eaten

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respectively, an additional p-channel transistor 26.

The operational amplifier operates as follows.

An input voltage is applied to the inputs of the operational amplifier, which in general has a differential and common-mode component. When the in-phase component of the input voltage is in the range

USS + Unas 8 + Upf p + Unac 10 UBX synf 1) DD - II) us 2 I - IUHac 4 I - Shpf p,

where onas 2 is the saturation voltage of the 1st transistor,

Uss is the voltage on the negative power rail;

UPF n - threshold voltage n-channel. transistors

1) dd voltage on positive power rail,

Unop p - threshold voltage of p-channel transistors, all transistors of both input differential stages are in saturation mode. Therefore, both input differential stages amplify the input voltage. The summation and amplification of the output voltages of the input differential stages is carried out by the first and second additional stages 13 and 16.

Thus, the amplified input voltage appears at the outputs of the device. This voltage is applied to the input of the common-mode voltage amplifier (STS). 19 The output voltage of the STD is fed to the gates of transistors 5 and 6 of the first dynamic load of the differential input stage 1. negative feedback on the common-mode output voltage. The operation of the OOS over the common-mode output voltage causes the output common-mode voltage to be equal to ochnostyu to Ref voltage cm alkaline audio USN voltage at terminal connected to the gate USN said fifth and fourth transistors 23 and 24. When the input voltage in-phase voltage component satisfies the conditions defined by the system of inequalities

USS + UHac 5 - I ipf p K UBX Sinf USS + + UHJC 8 + UHSC 10 + Unop n

U DD - UHac 12 I + ipf p UBX sync. U / U - I UHac2 I- I Unop pi- I UHac4 I, (2)

the differential pair transistors and the current generator of one of the input differential stages will not be in saturation mode, and, therefore, not

contribute to the input voltage gain. For example, if the first inequality of the system (2) occurs, the transistors of the differential pair and the current generator

The additional input differential stage 7 will be in unsaturated mode. If (2) is satisfied, then the operating currents change in silent mode of cascades 13 and 16. For example, if the first

0 inequality of the system (1), then the part of the quiescent current of the transistors 11 and 12. which flows through the transistors 9 and 10 in the case of (2), will flow through the transistors 17, 18, 15, 14, increasing their quiescent current. However, due to the action of the OOS at the common-mode output voltage, which is connected to the simplified system of state-of-the-art, 19, the change in the output common-mode voltage, which would have occurred without the presence of the OOS at the output

0 common mode voltage, will be suppressed. Thus, the operation of the proposed device will be maintained in the range of common mode voltage.

Uss UHac 5 - I Unop p I UBX synf idd- 5 - I UHac 2 I + Unop n (3)

Inequality (3) follows from the operating conditions of all transistors in at least one input differential stage in the saturation mode.

0Positive effect of the proposed

device compared with the prototype is a larger range of common-mode input voltages

Claims (1)

5 Formula of Invention An operational amplifier having a differential input and output containing an input differential cascade, made on the first and second p-channel transistors, with a current generator made on the p-transistor, the gate of which is connected to the first positive voltage reference bus, and the gate of the first p-channel transistor B5 is the inverting input of the device, the gate of the second p-channel transistor is a non-inverting input of the device, and their drain circuits are connected to the drains of the first and second n-channel transistors the first 0, the dynamic loads, respectively, whose sources are connected to the negative power bus and the gates are united, the common-mode voltage amplifier, made on the first and second differential 5 cascades formed by third and fourth p-channel transistors, with i current generator, made on p-channel transistor, and fifth and six p-channel transistors with current generator, made on p-channel transistor accordingly, the gates of the p-channel transistors of the current generators are connected to the first positive reference voltage bus, the gate of the third p-channel transistor is inverting, and the gate of the sixth p-channel transistor is the device's non-inverting outputs, respectively. The fifth p-channel transistors are connected and connected to the voltage bus equal to the desired common-mode voltage, the drains of the fourth and fifth p-channel transistors are combined and connected to the drain go n-channel transistor, which is the output of the common-mode voltage amplifier connected to its gate and connected to the combined gates of the n-channel transistors of the first dynamic load and the source of the seventh p-channel transistor and the drain of the third and sixth p-channel transistors with a negative power bus, characterized in that, in order to increase the range of the common-mode input voltage, an additional input differential stage is introduced, performed on n-channel transistors, some of them are combined with the gates of the p-channel transistors of the input differential cascade, and p-channel transistors of the second dynamic load, the sources of which are connected to the positive power supply bus, the gates are combined and connected to the first positive voltage reference bus, with a current generator made on an n-channel transistor, the gate of which is connected to the first negative voltage reference bus first and second additional cascades, with the first additional cascade performed on two p-channel transistors connected in a circuit with a common gate, the gates of which are connected and connected 5 to the second positive voltage reference bus, the sources are connected to the drains of the p-channel transistors of the second dynamic load, respectively, and the drains are connected to the third and sixth gates 0 p-channel transistors of the common-mode voltage amplifier, respectively, the second additional stage is made on two n-channel transistors, made according to the common-gate circuit, the gates 5 of which are connected and connected to the second negative voltage reference bus, the sources are connected to the drains of the n-channel transistors of the first dynamic load, respectively, and the drains are connected to the drain of the p-channel transistors of the first additional stage, respectively.