SU1672489A1 - Device to process the object images - Google Patents

Abstract

The invention relates to communications technology and can be used in digital image processing systems. The purpose of the invention is to increase the speed of the device. For this, the median selection block and the median code setting block are entered into the device. As a result, the delay value does not depend on the number of aperture elements. 4 il.

Description

The invention relates to communications technology and can be used in digital image processing systems, in particular for median filtering in order to suppress noise.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a diagram of the device; Fig 2 is a block sorting block diagram; Fig. 3 is a block diagram diagram for setting the median code; Fig. 4 is a block diagram diagram for selecting the median.

The device contains a television sensor 1, an analog-digital converter 2, an aperture shaping unit 3, a pulse generator 4, a code sorting unit 5, a median code setting unit 6, a median selection unit 7

The code sorting unit 5 contains n groups, each of which contains from O to (n - 1) comparison circuits 8 and memory block 9. The median code setting unit 6 contains n comparison circuits 10. The median selection unit 7 contains n formers 11 with the third state

The device works as follows: 3

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The video signal generated by the television sensor 1 is fed to analog-to-digital converter 2, where it is represented in digital form. From the output of the converter 2, the signal is fed to the input of the first shift register of the aperture imager of n pixels. When a pulse from the pulse generator 4 is input to the shift control input of the block 3, the pixel codes are sequentially shifted to form the n-element neighborhood of the current pixel. Codes of image elements from the outputs of block 3 in parallel arrive at the corresponding inputs of block 5 of code sorting. To determine the median of the sequence of numbers, it is used that the median rank is (n - 1) / 2 + 1, i.e. there is (n - 1) / 2 numbers in the sample is less than this.

The comparisons included in the block carry out a parallel comparison of all codes received at the input of the block. Comparison results are processed using

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memory blocks, each of which has a different programming than the others.

Consider determining the rank of a number with the sequence number m. There are (n - 1) comparison circuits, one of the inputs of which receives the selected number, with the first (ch - 1) comparison circuits receiving the second input, and therefore the signal to The output of these comparison schemes is 0. If the number with the sequence number m is greater than any of the numbers with the smaller order number. For the remaining (n - 1 - (t - 1) comparison circuits, a definable number is fed to the first input, and, therefore, the output signal of these comparison circuits is 1 if the number with the sequence number m is greater than any of the numbers with large sequence number. The output from these comparison circuits goes to the address inputs of the memory block with the sequence number m, which is programmed so that the data written to it is equal to the sum of zeros of the first (t - 1) address inputs plus the sum of ones by the remaining (n - 1) - (t - 1) inputs plus 1. The result obtained Is the rank of the given number.

The signals from the outputs of all n memory blocks are fed to the inputs of block 6 of the assignment of the median code, which compares the ranks of each of the n numbers in the neighborhood with the code corresponding to the allocated rank, which can be the rank of the median or any other rank. The first input of the comparison circuit with the sequence number t included in block 6 is followed by the rank code of the number with the sequence number m from the output of the corresponding memory block in block 5. This code is compared with the code of the rank being allocated to the second inputs of all comparison circuits of block 6: If the codes do not match, then at the output of the comparison circuit, we get O, if they match - 1. As a result, at the output of block 6, we get a position code, in one of the first digits of which 1, and in the rest ( - 1) bit O.

The positional code thus generated is fed respectively to the control inputs of the third-state shaper drivers located in the median selection unit 7. The data inputs of these drivers from the output of block 3 receives the codes of the neighborhood of the current decomposition element. Those drivers, whose information inputs contain a code different from the median, have control O at the input and, therefore, their output is in the third state. Shaper, on the information input of which there is a code. the corresponding median has control 1 at the input, and the output from the third state transmits the code of the median to the output of the block and the entire device.

Claims (1)

1. A device for processing images of objects containing television a sensor, the output of which is connected to the information input of the analogue-digital converter, the output of which is connected to the information input of the aperture forming unit, and a pulse generator, the output of which is connected to the clock inputs of the television sensor and analog-digital converter and the code sorting unit, the input of which is connected to the output aperture shaping unit, which is different from the fact that, in order to increase the device speed, the median selection block and the median code setting block are entered into it; Secondly, it is the device input, the information input of the median selection unit is connected to the output of the aperture shaping unit. the output of the code sorting unit-- with the information input of the median code setting unit, the output of which is connected to the control input of the median selection unit, the output of which is the output of the device. D. The device according to claim 1, wherein the code sorting unit contains n groups, each of which contains 0 to n - 1 comparison circuits, and a memory block, the first and second inputs of the comparison circuit with number k in the group m 1 k (n - m) are connected to the inputs of the rank determination unit. order numbers are m and (n -1-1 - k), the outputs of the memory blocks are the outputs of the block, the group with the number m (1 m n) contains n - m comparison circuits, the first and second inputs of the comparison circuit with the number k in the group m 1 k (n - m) are connected to the inputs of the block with the numbers m and (n 1 - k), all the n - 1 address inputs of the memory block in group m are connected to the outputs of all the comparison circuits in the yew group with c, - see comparison with the number (n 1 - t) in drush groups t j 1 gpf Z H Control input Fig.Z 77, U figm