SU1226500A1 - Device for processing object images - Google Patents

Abstract

This invention relates to technical cybernetics, in particular, to digital image processing systems. Improving the speed of the device is achieved by organizing pipeline processing of information using a group of elements AND, a block of sorting codes and a multiplexer. The proposed technical solution allows realizing the possibility of making the local neighborhood of the current image element of the desired shape and determining the median of the sequence of image elements belonging to the selected neighborhood. 1 3. p. F-crystals, 3 ill. Yu GCHO 05 cl

Description

This invention relates to technical cybernetics and can be used in digital image processing systems.

In particular, the proposed device can be used for median image filtering to suppress noise.

The purpose of the invention is to increase the speed of the device.

Figure 1 presents the block diagram of the proposed device; Figures 2 and 3 are examples of a specific embodiment of the control and sorting blocks, respectively.

The device contains a television sensor 1, such as a camera, analog-to-digital converter 2, a group of shift registers 3, generator 4 and ftp, group 5 of elements 6, the first register 7, control block 8, switch 9, for example a multiplexer second register 10 and block 11 code sorting, the first 12 and second 13 inputs of the device.

The control unit 8 (Fig. 2) contains a counter 14, which sets the register 15, the comparator -16 and the first loop of the delay elements 17.

The block and code sorting (fig.Z) contains the first group of comparators 18, the second group of comparators 19, BTOpyfc group of delay elements 20, the third group of delay elements 2, first 22 and second 23 delay elements, first 24, second 25 and third 26 groups of inputs unit and one input 27.

 The device works as follows.

Before the beginning of the median filtering of the input image, the mask code is written through the installed device input 12 to the register 7. This code determines the shape of the area (from the neighborhood of the current image element), using the elements of which the local median value of the sequence of image elements located within this range is calculated. areas. If the image element enters the neighborhood of the current image element, then the corresponding bit of the code written in register 7 is equal to G, otherwise this bit of the mask code is equal to O

From the setup input 13 of the device, the register 10 records the binary code of the number of the information input of the multiplexer 9, to which

the median code of the current sequence of image elements arrives. This number of the information input of multiplexer 9 depends on the contents of register 7.

The processed image in the process of its horizontal scanning by the camera 1 through the ADC 2 enters numerically to the input of the first shift register register group 3, When

The pulse generator 4 arrives at the shift control inputs of the shift registers 3 and sequentially shifts the pixel codes in the registers 3 to form a neighborhood of the current pixel of 3x3 dimensions.

Codes of the elements of the processed image from the outputs of the shift registers 3 in parallel arrive at the first inputs of elements of group 6, the second inputs of which simultaneously receive the values of the corresponding bits of register 7,

S .1 outputs of the elements And 6 groups 5

codes of the elements of the selected neighborhood of the image are in parallel received at the inputs of block 11. Block 11 performs parallel-sequential sorting of the input sequence of binary numbers - image elements.

It is known that calculating the median of a sequence of numbers is equivalent to sorting that sequence and choosing the sorted sequence of numbers as the median of the central element. Therefore, the calculation of the median of the image elements is performed by

1 1. In block 11, a pairwise parallel permutation of the input numbers is performed. To do this, serve the first and second groups of comparators, each of which has two information

an input, a control input, and two information codes. At the control input of the comparators 18 and 19, from the control unit 8, the signals for setting the comparators to the initial state are received before comparing each new pair of numbers.

As a result of parallel pairwise rearrangement of binary numbers on

the output of block 1I, codes of the sorted sequence of image elements are formed. Thus, block 11 implements a parallel exchange sorting algorithm. From the output of block I1, the codes of the sorted sequence of image elements are fed to the corresponding information inputs of the multiplexer 9, the control input of which from the output of the register 10 of the index receives the binary code of a given number. Multiplexer 9 and register 10 are used to select the current median image element from the sorted sequence of image elements at the output of block 11. Due to the fact that the number of nonzero bits of register 7 is generally not equal to n, the median element is not the central element of the sorted binary sequence. the numbers at the output of block 11, i.e. does not have a number (n-1) / 2. Since the pixels are whole binary numbers, the median element has the number (N + l) / 2 in the sorted number sequence at the beginning of the numbering from the maximum number of this sequence (where N is the number of non-zero register bits 7).

Block 8 is used in the proposed device to control the process of sorting the sequence of image elements in block 11. Clock pulses from the output of generator A are fed to the counting input of counter 1D. Comparator 16 compares the code for the number of clock pulses counted in counter 14 and the code for the number of bits of the input image elements, which is recorded in register 15. If the codes are equal, the input I appears at the output of the comparator 16. the first output of the control unit and through the delay elements 1 7 to the remaining outputs of the block 8. The signals 1 at the outputs of the block 8 determine the ends of the successive codes of the picture elements, which are fed to the control inputs of the corresponding nodes of the block 11. Signal Al 1 from the output of the comparator 16 also enters the reset input of the counter .14 and sets it to the zero state. Delay time

26,500

The delay element 17 in block 8 is equal to the delay time of delay elements 20 to 23 in block 11, which, in turn, is determined by the delay time of the comparators 18 and 19.

Claims (2)

1. Device for processing images of objects containing television. a zion sensor, whose input is connected to a pulse generator, and the output is connected to one input of an analog-digital converter, the other 15 whose input is connected to a pulse generator, and the output is connected to one input of the first register of serially connected shift registers of the group, the other inputs of which are connected to the pulse generator, and the outputs are connected to one input of the AND elements of the group, the other inputs of which are connected to the outputs of the first register which input is the first 25 input device, a counter, one input of which is connected to the pulse generator, and the output is connected to one input of the comparator, the other input of which is connected to the master switch-. 30, and the output is connected to another counter input, and the series-connected delay elements of the first group are connected, the first delay element of the first group is connected to the output of the comparator, and the switch, is different from the fact that, in order to increase the speed of the device, it contains a code sorting unit whose inputs are connected 40 with the outputs of the AND group elements, the comparator and the delay elements of the first group, and the outputs are connected to the inputs of the switch, the output of which is the output of the device, and the second register, The 45 input of which is the second input of the device, and the output is connected to the control input of the switch. 2. The device according to claim 1, characterized in that the code sorting unit comprises a first group of series-connected comparators, one of the inputs of which are the inputs of the first group of inputs of the block, the second group of serially connected comparators, one of the inputs of which are the inputs of the first group of inputs block, the second and third groups of delay elements, inputs and outputs 51226500 which are connected to the inputs and exited by one output of the block, while giving the respective comparators the first inputs of the first comparators of the first and The second groups are the inputs of the first and second groups of block inputs, and the other 5 inputs and outputs of the corresponding comparators of the first and second groups are connected to the inputs and outputs of the corresponding comparators of the second and first groups, respectively. first and second groups, the first delay element, the input of which is one block input, and the output of the transmitter to the second comparator of the second group, the second delay element, whose input is connected to the output of the last comparator of the second group, and the output