SU1672436A1 - Data color display unit - Google Patents

Abstract

The invention relates to computing and can be used in personal computers as an interface for a color alphanumeric display. The purpose of the invention is to provide the possibility of programmatically controlling the color of each displayed symbol and the surrounding background. The goal is achieved by introducing into the known device an additional controller, a memory unit, a switch, two decoders and a key block. An additional storage unit is used to store the numeric character and background attributes. The additional controller works synchronously with the main one in the information output mode. When unloading the main and additional controllers operate in parallel. The device allows you to display up to 256 different characters - upper and lower case letters of the Russian and Latin alphabet, numbers, punctuation and pseudographic characters. The color palette of the displayed characters and the background can contain up to 8 different colors. Both palettes are independent. 1 il.

Description

The invention relates to computing and can be used in personal computers as an interface for a color alphanumeric display.

The purpose of the invention is to provide the possibility of programmatically controlling the color of each output symbol and the surrounding background.

The drawing shows the scheme of the proposed device

The device contains the first 1 and second 2 memory blocks, the first 3 and second 4 decoders, the address bus 5, the memory controller 6, the first 7 and second 8 controllers

output, local data bus 9, data bus 10, key block 11, character generator 12, register 13, switch 14. The first and second memory blocks are storage devices with random access, respectively, of the display area and color attributes. The memory controller can be executed on the basis of the BIS Kr 580BT57 in the standard power on. Output controllers are BIS Cr 580BG75 in standard power up.

The device works as follows.

In the process of operation, the external computer loads into the memory block 1 a seven-bit information VI th

4 CO O

The text of the characters that should be displayed on the screen. Information on the state of the eighth bit of the character code and the color of the character is loaded into memory block 2. Using decoders 3 and 4, blocks 1 and 2 are separated into non-intersecting areas of the VM address space, which allows access to any of the memory cells of each memory block. Block 11 connects the local 8-bit bus 9 to the data bus 10 of the computer. The enable inputs of the controllers 7 and 8 are interconnected. As a result, the same-name registers of both controllers are located at the same addresses in the address space. Therefore, when initializing the controllers, the same information is written into their control registers, which ensures synchronous operation of the controllers. Only the main controller 7 registers are available for reading the computer. Allowing the operation of the controllers 7 and 8 in the same way as controller 6 is carried out using the decoder of computer input-output devices (not shown in the drawing). Each of the controllers 7 and 8 has a buffer RAM, which must be filled with information before starting the display of the next line. The filling is carried out using the controller b. To this end, at the output of the DRQ controllers 7 and 8, a request is made for the RAP cycle, during which information from memory blocks 1 and 2 should be written to the controllers 7 and 8. The said signal from the output of the controller 7 requests the controller 6, which pauses The computer and, having received confirmation of the resolution of the PDL cycle from the last, notifies controllers 7 and 8 with the signal D ACK (active level is low). At the same time, the DACK signal is fed to the resolution of the address decoder 4 and to block 11. When the signal is sent to the decoder 4, the address space occupied by blocks 1 and 2 of the memory is combined in the address area of block 1. Simultaneously, block 11 turns off the local 8 -discharge bus 9 from data bus 10 computers. The data bus of the device for the time of the PDU cycle is thus transformed into a 16-bit one, to one half of which memory block 1 and controller 7 are connected, and to the second - memory block 2 and controller 8. Due to such a rearrangement, it becomes possible to cycle the PDU simultaneously enter the necessary information into the internal buffer RAM of both controllers. After the end of the FPD cycle, the DACK signal assumes the level of a logical unit, an 8-bit device data bus structure is restored. The process of displaying information by the controllers 7 and 8 begins. The information from the output of the controller 7, supplemented

deduced at the same time by the controller 8 bit and recoded by the character generator 12, is fed to the shift register 13, which is followed by its bitwise shift. Logic unit output

the shift register corresponds to the displayed symbol, the logical zero to the background on which the symbol is formed. The six remaining information outputs of the controller 8 are connected to the inputs of the switch 14. These signals output simultaneously with the character codes carry information for all three electronic projectors of the color ELG display - three bits about the color of the output symbol and three bits about the color

the background on which the symbol is formed On the three outputs of the switch 14, depending on the output state of the shift register 13 connected to its control input, either bits are present that specify

the color of the symbol, or bits that set the background color. The video signals generated in this way at these three outputs are used to control the color ELG electronic searchlights.

Device for displaying information on

The color display screen allows you to display up to 256 different characters - upper and lower case letters of the Russian and Latin alphabet, numbers, punctuation marks, and 70-80 pseudographic characters. In addition, the color palette of the displayed characters can contain up to 8 different colors, the same color can contain the color palette of the background, and both palettes

are completely independent.

Claims (1)

Invention Formula A device for outputting information to a color display screen comprising the first memory block, the memory controller, the first output controller, the character generator, the register, the address inputs-outputs of the memory controller are the address inputs of the device, the inputs of the first memory block are connected to the address inputs- the low-order outputs of the memory controller, the information inputs of the first output controller are connected to the information inputs-outputs of the memory controller and the first memory block and are the information inputs of the device, the inputs The resolutions of the first output controller and the memory controller are respectively the first and second device synchronization inputs, the confirmation output of the memory controller is connected to the confirmation input of the first output controller, the request output of which is connected to the request input of the memory controller, the first output controller outputs are connected to the lower character generator bits, the outputs of which are connected to the information inputs of the register, the synchronization input of which is the synchronization input of the device, the input input Determinations and the output of the request of the memory controller are respectively the fourth synchronization input and the output of the device synchronization, characterized in that, in order to enable the programmable control of the colors of each output symbol and the surrounding background, a second memory block, a second output controller, a switch are inserted into it , a key block and two decoders, the register output is connected to the control input of the switch, the outputs of the second output controller group are connected to the information inputs of the switch, the outputs of which are the information outputs of the device, the inputs of the first decoder, the information inputs of the first and second decoders are connected to the address inputs and outputs of the higher bits of the memory controller, the address inputs of the second memory block are connected to the address inputs of the first memory block, the information inputs of the key block are connected to memory controller information inputs / outputs, outputs the key block is connected to the information inputs of the second memory block and the information inputs / outputs of the second output controller, the resolution input of which is connected to the resolution input the first output controller, the control input of the second decoder, the confirmation input of the second output controller, and the control input of the key block are connected to the confirmation output of the memory controller, the output of the second decoder is connected to the enable input of the second memory block, the output of the second output controller is connected to the higher bit input character generator, the output of the first decoder connected to the enable input of the first memory block. TO REC display