GB2284131A

GB2284131A - Video display apparatus

Info

Publication number: GB2284131A
Application number: GB9322827A
Authority: GB
Inventors: Yiu Cho Chung; Hon Yee Wong; Hong Wa Poon; Chi Keung Tang; Kwok Yiu Leung; Ngai Wa Wong; Chiu Fan Kwong
Original assignee: Hong Kong Productivity Council
Current assignee: Hong Kong Productivity Council
Priority date: 1993-11-05
Filing date: 1993-11-05
Publication date: 1995-05-24
Also published as: GB9322827D0

Abstract

A video display apparatus comprises a display unit 1, a video memory unit 2 and a display controller 3. The display controller 3 includes a data compression and expansion ("compansion") circuit 4 and the video memory unit 2 includes a compressed screen buffer 5. In a "screen frozen" mode in which video data supplied to the apparatus are unchanged, the data "compansion" circuit 4 compresses the supplied video data which is then stored in the compressed buffer 5. In a refresh operation, the display controller 3 retrieves the compressed data from the compressed screen buffer 5, the data "compansion" circuit 4 expands the data, and the display controller 3 processes the expanded data before passing it to the display unit 1. The power consumed is greatly reduced as compared with a conventional apparatus due to the reduced inter-module data traffic. Further aspects are also described in which inter-module data traffic is also reduced. <IMAGE>

Description

VIDEO DISPLAY APPARATUS The present invention relates to a video display apparatus, and more particularly to a computer video display subsystem.

An example of a known computer display subsystem is shown in Figure 1. It consists of a display unit 1, which may be an LCD module, a CRT unit, or any other display unit requiring a periodic refresh process in order to maintain a stable (flicker-free) screen; a video memory unit 2 which may be a VRAM or any other storage device able to hold video data; and a display controller 3, the major functions of which are to periodically retrieve video data from the video memory unit 2, translate it into a display signal and pass the display signal to the display unit 1 to achieve the screen refresh function; and to interface with the CPU of the computer to receive new video data and pass it to the video memory unit 2 without affecting the display unit 1.

The known computer display subsystem operates either in a "screen changing" mode in which the screen display changes in accordance with new data stored in the video memory unit 2, or in a "screen frozen" mode in which both the screen display and the data in the video memory unit 1 are unchanged. For refreshing purposes in the "screen frozen" mode, the display controller 3 still retrieves video data from the video memory unit 2 and translates it into a display signal for every pixel to be displayed on the screen. For example, if the screen supports 16 colours and has 640 x 480 pixels, each pixel requires half a byte of video data and each frame refresh requires 640 x 480 x 0.5 = 153600 bytes.During this process, the video memory unit 2 and the display controller 3, which are normally CMOS devices, consume power in an amount proportional to the square of the supply voltage, to the frequency of toggling and to the capacitative loading of the CMOS circuits. This capacitative loading is very high at the video memory address bus and the data bus, via which buses the video memory unit 2 and the display controller 3 communicate, as compared with the internal capacitative loading of the display controller 3. Since the subsystem operates in the "screen frozen" mode for more than 80% of the time, it is clear that a relatively large amount of power is wasted when the display controller 3 accesses the video memory unit 2 to retrieve unchanged video data.

Because the different types of display unit, for example LCD and CRT, employ entirely different technologies, it is impractical to devise a common method of reducing the power consumed by the display unit.

It is therefore an object of the invention to provide a video display apparatus in which the video memory unit and the display controller consume less power than they normally consume in conventional apparatus.

From a first aspect, the invention consists in a video display apparatus comprising means for storing video data, display control means, a display unit for displaying data which correspond to stored video data, data compression and expansion means, and means for storing compressed video data, said data compression means being arranged to compress supplied video data, and the apparatus being operable to enter the compressed data into said compressed data storage means and to retrieve said compressed data from said compressed data storage means, said data expansion means being operable to expand said retrieved data.

Preferably, said compressed data storage means forms part of said video data storage means. Said data compression and expansion means may comprise a data compression and expansion circuit which forms part of said display control means. Alternatively, said data compression and expansion means may comprise a separate data compression circuit and a data expansion circuit which forms part of said display control means.

The apparatus may be operable either in a first mode in which said supplied video data are changed or a second mode in which said supplied video data are unchanged, said data compression and expansion means being operative in said first or second mode. In said first mode, said display control means may be operable to enter said supplied video data into said video data storage means and, in a refresh operation, to retrieve said supplied data and to process it in order to obtain said corresponding data for said display unit and in said second mode, said display control means may be operable to process the expanded data in order to obtain said corresponding data for said display unit.

From a second aspect, the invention consists in a video display apparatus comprising means for storing video data, display control means, a display unit for displaying an array of pixels, the array being made up of a plurality of blocks, each containing one or more of said pixels, block storage means for storing video data to which the pixel information of one block corresponds, and means for indicating if the pixel information of each block in succession is different from the pixel information of the block previously assessed by the display control means, said apparatus being operable to retrieve video data corresponding to said different pixel information from said video data storage means and to store said retrieved video data in said block storage means.

Said indicating means may comprise a plurality of delta flags each corresponding to one of the blocks, each delta flag having a specific value if the pixel information contained in the corresponding block is identical to that of the block previously assessed by the display control means, and another specific value if it is different, the value of the first delta flag being determined according to the last block of the previous frame or any specific value.

Said delta flags may be stored in a delta flag storage means.

Preferably, said block storage means forms part of said display control means, and preferably said delta flag storage means forms part of said video data storage means.

The apparatus may be operable either in a first mode in which supplied video data are changed or a second mode in which said supplied video data are unchanged, said block storage means being operative in said first or second mode.

In said first mode, said display control means may be operable to enter said supplied video data into said video data storage means and, in a refresh operation, to retrieve said supplied data and to process it in order to obtain said array of pixels. In said second mode, said display control means may be operable to process the data contained in said block storage means in order to obtain said array of pixels.

From a third aspect, the invention consists in a video display apparatus comprising means for storing video data, display control means, a display unit for displaying an array of lines of text which correspond to stored video data, and line storage means for storing information corresponding to one line of text, said line storage means being arranged to store in turn information corresponding to successive lines of the array, said display control means being arranged to process a combination of information retrieved from the line storage means and data retrieved from the video data storage means into a format required by said display unit.

The information stored in said line storage means may consist of character defining codes for one line of text.

The data retrieved from the video data storage means may consist of font pattern data.

Preferably, said line storage means forms part of said display control means.

The apparatus may be operable either in a first mode in which video data supplied thereto are changed or a second mode in which said supplied video data are unchanged, said line storage means being operative in said first or second mode. In said first mode, said display control means may be operable to enter said supplied video data into said video data storage means and, in a refresh operation, to retrieve said supplied data and to process it into a format using which said display unit can display said array.

Said display control means may be provided with font pattern generation means which is able to generate the font pattern data of frequently used characters in a refresh operation in said second mode, said display control means being arranged to retrieve the font pattern data of rarely used characters from the video data storage means.

From a fourth aspect, the invention consists in a video display apparatus comprising means for storing video data, display control means and a display unit for displaying an array comprising successive pairs or groups of identical lines of pixels, the display control means being arranged such that pixel data supplied by the display control means to the display unit in order to display one line of each pair or group is also used by the display unit to display the other line or lines of each pair or group.

Said display control means may be arranged to control said display unit such that pixel data is latched from a shift register of said display unit to a display driver thereof once for one line of each pair or group and again for the other line or lines of each pair or group.

The invention will be described by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram of a known video display apparatus; Figure 2 is a block diagram of a video display apparatus according to one embodiment of the first aspect of the invention; Figure 3 is a block diagram of a video display apparatus according to one embodiment of the second aspect of the invention; Figure 4 shows an array displayed by a video display apparatus shown in Figure 3; Figure 5 is a block diagram of a video display apparatus according to one embodiment of the third aspect of the invention; Figure 6 is a block diagram of a known display unit for use with a video display apparatus according to one embodiment of the fourth aspect of the invention; and Figure 7 is a timing diagram showing the operation of the display unit shown in Figure 6.

Figure 2 shows a video display apparatus or computer display subsystem according to one embodiment of the first aspect of the invention in which the reference numerals 1-3 designate the same components as in Figure 1. In the "screen changing" mode the subsystem of Figure 2 operates in the same manner as the known system shown in Figure 1.

The display controller 3 contains a data compression and expansion (hereinafter "compansion") circuit 4 and the video memory unit 2 contains a compressed screen buffer 5.

During the first frame refresh after the subsystem changes from the "screen changing" mode to the "screen frozen" mode, the display controller 3, as well as performing a conventional refresh operation, compresses the video data for the frozen screen using the data "compansion" circuit 4 and transfers the compressed data to the compressed screen buffer 5. The refresh and compression operations normally require the same length of time.

During subsequent refresh operations, the display controller 3 retrieves compressed data from the compressed screen buffer 5 and expands this data using the "compansion" circuit 4, before translating the expanded data as usual.

The "compansion" circuit may for example use run length or Huffman data compression algorithms. The "compans ion" circuit 4 may also operate in the "screen changing" mode.

In an alternative embodiment of the first aspect of the invention, a data compression circuit is implemented outside of the display controller. Data compression is done at the CPU of the system through the execution of some data compression software programmes, while a data expansion circuit is implemented within the display controller.

Figure 3 shows a computer display subsystem according to one embodiment of the second aspect of the invention.

The display controller 3 contains a block buffer 9 and the video memory unit 2 contains a delta flag buffer 10.

Figure 4 shows how the screen of the display unit 1 is notionally divided into a number of blocks. The blocks have a maximum size of the entire screen and a minimum size of one pixel. The block buffer 9 is able to store video data corresponding to one of the blocks. The delta flag buffer 10 contains as many delta flags as there are blocks, each flag having a value of either 0 or 1.

In the first refresh operation of a "screen frozen" period, the delta flags are set to values according to the pixel information contents of the corresponding blocks.

The value of flag 1 may be determined according to the last block of the previous frame; alternatively, flag 1 may always have a value of 1. Flag N is given a value of 0 when the contents of block N are identical to those of block N-1, and a value of 1 when these two blocks have different contents.

In the second and subsequent refresh operations, the display controller 3 reads each delta flag from the delta flag buffer 10. If a delta flag has a value of 1, the display controller 3 fetches the video data for the corresponding block from the video memory unit 2, translates or processes the data as usual and updates the block buffer 9. If the value of the delta flag is 0, the display controller 3 simply processes the video data in the block buffer 9 and sends it directly to the display unit 1.

The above delta flag values may alternatively be reversed, flag N having a value of 1 if the contents of block N are identical to those of block N-l and a value of 0 when these two blocks have different contents. Whilst figure 4 shows one particular scheme for numbering the blocks, block N-1 may be on the left, on the right, or in any other position relative to block N.

The block buffer 9 and delta flag buffer 10 may also operate in the "screen changing" mode.

Figure 5 shows a display subsystem according to one embodiment of the third aspect of the invention which is used for text displays and has a display controller 3 including a line buffer 6. This line buffer 6 stores the character defining codes (ASCII codes and attribute codes) for one line of text. In a refresh operation, the display controller 3 retrieves the character defining codes from the line buffer 6 and the corresponding font pattern data from the video memory unit 2. The data is processed as usual.

The display controller of the embodiment of Figure 5 also includes a small number of programmable character font generators. These font generators are used to generate font pattern data for the most frequently used characters, such as space, "a", "t" etc. Whenever the defining codes for these characters are encountered, the display controller uses its internal store of generated font patterns rather than retrieving the font pattern data from the video memory unit.

A computer display subsystem according to an embodiment of the fourth aspect of the invention is used in socalled multiple scan applications where the character height of a display is multiplied by M, M being any integer greater than or equal to 2, by repeating the video data corresponding to every Mth pixel line for the following M-l pixel lines. Many conventional LCD controllers support such an application, by which for example, a display of 640 x 200 pixels has its resolution decreased to 640 x 100, with M=2.

Figure 6 shows a typical 640 x 200 resolution LCD display module including column drivers 7 and row drivers 8. The table below describes the functionality of the signals input to the LCD module.

Name i I/O | Description lr DIN nlne :N or Frame signal siniies the start scan IYSCL --- new LCD frame.

IN Row Latch Pulse - use to generate the LCD driving signals for each line.

LP IN Column Latch Pulse - latch clock of the data from the LCD shift register to the display driver register.

XSCL IN T LCD data shift clock.

Doc0..3 IN Video display data input to the J LCD module which is in 4 bits width.

Each column driver consists of a display driver situated in front of a set of shift registers. The LCD shift clock XSCL shifts data in 4 bit words on the lines D[0..3] into the shift registers and the YSCL signal latches the data from the shift registers to the display drivers.

The display controller according to the embodiment of the fourth aspect of the invention controls the LP and the YSCL signals separately. For each LP pulse, two YSCL pulses are generated which produce LCD driving signals for the odd-numbered pixel line and the identical following even-numbered pixel line.

Each aspect of the invention thus greatly reduces the power consumed by a computer display subsystem by reducing the inter-module data traffic.

The subsystem according to the first aspect of the invention can for example use a linear Huffman compression algorithm with a compression ratio of about six to reduce the number of times the video memory unit 2 is accessed to about 17% of the number required by a conventional subsystem. The power required for the compression and expansion of the video data on-the-fly, which takes place inside the display controller 3, is very small compared to the power consumed by the external memory access process. Therefore this subsystem will consume essentially 17 of the power consumed by the conventional subsystem.

In a conventional VGA (video graphics adaptor) screen with 64K colour, the resolution is 640 x 480 pixels and each frame refresh requires 640 x 480 x 2 = 614400 bytes of data from the video memory. In contrast, in the invention according to the second aspect, the delta flag buffer scheme, with a block size of one pixel, in the best case of a blank screen, requires 640 x 480 x (1/8) = 38400 bytes of data from per frame, or 6% of the conventional value. Thus with the blank screen a power saving greater than 90% will be achieved. Screen contents often include repeating patterns, giving a significant saving in video data access and, accordingly, in power.

To calculate the power saved by the line buffer scheme of the third aspect of the invention the amount of data accessed from the video memory per refresh frame can be compared with the amount required by a standard VGA system.

In the latter, each character has approximately 480/25 = 19 pixel lines. Each character requires 3 bytes of data per pixel line, 2 bytes for character definition and 1 byte for font pattern. There are 80 characters in a line of text and so each frame requires 80 x 3 x 19 x 25 = 114000 bytes of data. In the line buffer scheme, the line buffer stores the character definition data for one line of text which amounts to 80 x 2 = 160 bytes. Since only the font pattern data is fetched from the video memory once the line buffer is full, the amount of data accessed per frame is reduced to (80 x 2 + 19 x 80) x 25 = 42000 bytes or less than 37% of the conventional data. This figure is approximately halved by the use of programmable character font generators for frequently used characters which may take up 50% of a normal screen.The resulting power consumption may be about 188 of the conventional value.

The video display apparatus according to the fourth aspect of the invention divides by M the data needed to be retrieved from the video memory by a conventional subsystem operating in multiple scan mode, since data is only retrieved for every other pixel line. The power consumption can accordingly be reduced by 50% if M=2.

The extra logic circuits required by each aspect of the invention are relatively simple and can be added to the integrated circuits of a conventional VGA display system whilst only increasing the silicon area by approximately 10% depending on the type of display controller used. For example, the increased silicon area may only be about 3 to 6% or it may be more than 10%. Also, no significant increase in the number of 1/0 pins is required, and so the manufacturing cost of the subsystems according to the invention is close to that of the conventional subsystem.

Although specific embodiments of the invention have been described, it will be envisaged that modifications may be made without departing from the scope of the invention.

For example the extra logic circuits (the data compansion circuit and compressed screen buffer of the first aspect of the invention, the block buffer and delta flag buffer of the second aspect and the line buffer of the third aspect) may be provided externally of the display controller and the video memory unit rather than being contained therein.

Claims

1. A video display apparatus comprising means for storing video data, display control means, a display unit for displaying data which correspond to stored video data, data compression and expansion means, and means for storing compressed video data, said data compression means being arranged to compress supplied video data, and the apparatus being operable to enter the compressed data into said compressed data storage means to retrieve said compressed data from said compressed data storage means, said data expansion means being then operable to expand said retrieved data.

2. A video display apparatus as claimed in claim 1, wherein said compressed data storage means forms part of said video data storage means.

3. A video display apparatus as claimed in claim 1 or 2, wherein said data compression and expansion means comprises a data compression and expansion circuit which forms part of said display control means.

4. A video display apparatus as claimed in claim 1 or 2, wherein said data compression and expansion means comprises a separate data compression circuit and a data expansion circuit which forms part of said display control means.

5. A video display apparatus as claimed in any preceding claim, wherein said apparatus is operable either in a first mode in which said supplied video data are changed or a second mode in which said supplied video data are unchanged, said data compression and expansion means being operative in said first or second mode.

6. A video display apparatus as claimed in claim 5, wherein, in said first mode, said display control means is operable to enter said supplied video data into said video data storage means and, in a refresh operation, to retrieve said supplied data and to process it in order to obtain said corresponding data for said display unit.

7. A video display apparatus as claimed in claim 5 or 6, wherein, in said second mode, said display control means is operable to process the expanded data in order to obtain said corresponding data for said display unit.

8. A video display apparatus comprising means for storing video data, display control means, a display unit for displaying an array of pixels, the array being made up of a plurality of blocks each containing one or more of said pixels, block storage means for storing video data to which the pixel information of one block corresponds, and means for indicating if the pixel information of each block in success ion is different from the pixel information of the block previously assessed by the display control means, said apparatus being operable to retrieve video data corresponding to said different pixel information from said video data storage means and to store said retrieved video data in said block storage means.

9. A video display apparatus as claimed in claim 7, wherein said indicating means comprises a plurality of delta flags each corresponding to one of the blocks, each delta flag having a specific value if the pixel information contained in the corresponding block is identical to that of the block previously assessed by the display control means, and another specific value if it is different, determined according to the last block of the previous frame of display or any specific value.

10. A video display apparatus as claimed in claim 9, wherein said delta flags are stored in a delta flag storage means.

11. A video display apparatus as claimed in claim 10, wherein said delta flag storage means forms part of said video data storage means.

12. A video display apparatus as claimed in any of claims 8 to 11, wherein said block storage means forms part of said display control means.

13. A video display apparatus as claimed in any one of claims 8 to 12, wherein said apparatus is operable either in a first mode in which supplied video data are changed or a second mode in which said supplied video data are unchanged, said block storage means being operative in said first or second mode.

14. A video display apparatus as claimed in claim 13, wherein, in said first mode, said display control means is operable to enter said supplied video data into said video data storage means and, in a refresh operation, to retrieve said supplied data and to process it in order to obtain said array of pixels.

15. A video display apparatus as claimed in claim 13 or 14, wherein, in said second mode, said display control means is operable to process the data contained in said block storage means in order to obtain said array of pixels.

16. A video display apparatus comprising means for storing video data, display control means, a display unit for displaying an array of lines of text which correspond to stored video data, and line storage means for storing information corresponding to one line of text, said line storage means being arranged to store in turn information corresponding to successive lines of the array, and said display control means being arranged-to process a combination of information retrieved from the line storage means and data retrieved from the video data storage means into a format required by said display unit.

17. A video display apparatus as claimed in claim 16, wherein the information stored in said line storage means consists of character defining codes for one line of text.

18. A video display apparatus as claimed in claim 16 or 17, wherein the data retrieved from the video data storage means consists of font pattern data.

19. A video display apparatus as claimed in claim 16, 17 or 18, wherein said line storage means forms part of said display control means.

20. A video display apparatus as claimed in any of claims 16 to 19, wherein said apparatus is operable either in a first mode in which video data supplied thereto are changed or a second mode in which said supplied video data are unchanged, said line storage means being operative in said first or second mode.

21. A video display apparatus as claimed in claim 20, wherein, in said first mode, said display control means is operable to enter said supplied video data into said video data storage means and, in a refresh operation, to retrieve said supplied data and to process it into a format using which said display unit can display said array.

22. A video display apparatus as claimed in any one of claims 16 to 20, wherein said display control means is provided with font pattern generation means which is able to generate the font pattern data of frequently used characters in a refresh operation in said second mode, said display control means being arranged to retrieve. the font pattern data of rarely used characters from the video data storage means.

23. A video display apparatus comprising means for storing video data, display control means and a display unit for displaying an array comprising successive pairs or groups of identical lines of pixels, the display control means being arranged such that pixel data supplied by the display control means to the display unit in order to display one line of each pair or group is also used by the display unit to display the other line or lines of each pair or group.

24. A video display apparatus as claimed in claim 23, wherein said display control means is arranged to control said display unit such that pixel data is latched from a shift register of said display unit to a display driver thereof once for one line of each pair or group and again for the other line or lines of each pair or group.

25. A video display apparatus substantially as herein described with reference to Figure 2 or Figures 3 and 4 or Figure 5 or Figures 6 and 7 of the accompanying drawings.