SU1670667A1 - Device for checking number of frames in camera - Google Patents

Abstract

The invention relates to devices for controlling technological processes, in particular, to devices for processing information about the number of frames used in special cameras. The purpose of the invention is to increase the functionality by reducing the time for correcting information and improving the reliability of operation by increasing the noise immunity of the device. The device allows you to quickly correct the information separately on each counter 8, 9, 10, control it on the indicator 14, and eliminate errors when correcting the information in conditions determined by lack of time. The device provides a warning signal of the zero state of the frame counter. The device has high noise immunity due to the introduction of an analyzer of the input signal reliability. 2 Il.

Description

About VJ

About About About vj

1

The invention relates to devices for controlling technological processes, in particular, to devices for processing information about the number of frames used in special cameras.

The aim of the invention is to increase the functionality by reducing information correction time and improving the reliability of operation by increasing the noise immunity of the device.

Figure 1 shows the functional diagram of the device for three meters; 2 is a timing diagram of the operation of the device.

The device contains unit 1 frames with driver 2 input signal at the output. The unit number of the counter 3 is connected to the input of the shift register 4. the outputs of which are connected to the first inputs of the valves 5-7 of the correction resolution The outputs of the valves 5-7 are connected respectively to the enabling inputs of the counters 8-10, the outputs of which are connected to the decoders 11-13, connected to the outputs display unit 14. One of the inputs of the mode selection unit 15 is connected to the output of the OR element 16. The counting input of the auxiliary counter 17 is connected to one of the outputs of the frequency divider 18, the input of which is connected to the output of the pulse generator 19. The device also contains a correction frequency multiplexer 20, a signal switch 21, a corrected counter selector valve 22-24, a decoder 25 zero readings with an output signal generator 26 and an input signal analyzer 27, a counter trigger signal driver 28.

The device works as follows.

Before work is started automatically or by the operator, the initial information on the initial number of frames of the film is entered by the signals of the setpoint controller 3, 28. To record the initial number of frames, first select the counter 8-10, the information from which must be corrected. Depending on the number of pulses coming from the dial of the counter number 3, a signal is generated at the corresponding output of the shift register 4, which through the OR 16 gate prepares the mode selection unit 15 for operation. At the first impulse of the dial of the set number of the counter 3 through the valve 7 in the presence of an enabling signal from the output of the mode selector 15, the low counter 8 is selected for correction, with the second through the gate 6 of the counter 9. when the third press through the gate 5, the estimator 10. returns the shift register 4 to the initial state (detects em) and subsequent

impulses, the process of selecting the level being adjusted is similar to

The inputs of the valves 22-24 select the adjustable counter receives the enabling signal from the corresponding output

shift register 4 and the signal from the output of the splitter 18 frequency (for example, 2 Hz), resulting in a signal from the output of one of the gates 22-24 affects the corresponding decoder 11-13 which leads to

blinking the information selected for correction on the display of the display unit 14, while no pre-set or remaining information is lost

Directly entering information into the counter selected for correction (a visual indication of its flashing on the display unit of the display unit 14) starts when the enable signal from the generator 28 is present. The mode selection unit 15 switches and the enable signal from its output goes to the second gate inputs 5-7. and the input of the switch 21 signals, the signal of which rtzvryzugs direct communication between the counters 8-10

The signal from the output of the mode selection unit 15 is maintained until the correction process is completed, i.e. not shifting the register 4.

The signal of the mode selection unit 15 switches the signal switch 21 to the transmission of signals from the output of the multiplexer 20 correction frequency. The inputs of the multiplexer 20 correction frequency receive CHI generator oscillations of 19 pulses, converted by divider 18 into the grid of necessary frequencies (for example, a frequency of 1.2, 16 Hz), and an auxiliary counter of 17 pulses,

which begins to function in the presence of an enabling signal from the generator 28 of the counter trigger signal, forms a control code (see Fig. 2) arriving at the control inputs of the multiplexer 20 correction frequency. The control input is organized in such a way (by selecting the appropriate weight values of the bits of counter 17) that the signals of the following algorithm (taking into account the grid values of the divider frequency 18) are passed to the output of the correction frequency multiplexer 20 - the first six pulses with a following frequency 1 Hz, then four pulses with a frequency of 2 Hz, then to the end of the action

the signal from the driver 28 pulses with a frequency of 16 Hz.

The signal thus generated through the signal switch 21 is fed to the counting input of the selected counter 8-10, to the enabling input of which a signal is supplied from the corresponding valve 5-7. The change of information in the correction mode in the selected counter and on the display unit 14 will be carried out in the forward direction with the corresponding frequency. The first b c in the counter selected for correction, the information will change at a frequency of 1 Hz, then the frequency will be sequentially changed to a value of 2 and 16 Hz. Higher frequencies compared to the main 1 Hz (2 and 16 Hz) are used when a significant number of pulses are entered into the corrected counter (for example, when entering from zero readings to readings more than 10 to 99 inclusive), which speeds up the process of entering initial information . Interrupting and subsequently sending a signal from the imaging unit 28 at any time returns the device to work with a low (1 Hz) correction frequency, which makes it possible to avoid errors at the final stage of entering information into the selected counting stage.

Similarly, the source information is entered into all counters. In this case, on the indicator of the display 14 for the entire correction time of the indications of the initial information the symbol is displayed - a sign of the correction, which is controlled by the signal from the output of the block 15.

At the end of the entry of the initial information (i.e., the register 4 was reset) the device goes into operation. In this case, the signal from block 15 through the signal switch 21 connects the direct connections between counters 8-10, the control inputs of which receive a signal of the counting mode, and on the indicator of block 14, the symbol changes and the symbol characterizes the operating mode.

The input signal from setpoint 1 is fed to the input of the imaging unit 2, which converts its level, and is further processed in the analyzer 27 for input signal reliability. Analyzer 27 is a threshold device with a measure of the duration of the input signal. In this case, if the duration of the signal from block 2 is less than the time required to form the signal, the input signal is taken as false and is not passed through the analyzer 27. If the duration

input signal is such, then the signal at the output of the analyzer 27 has time to be formed, that in the presence of a permitting signal from the decoder 25 at the output of the analyzer

27, a signal is generated that arrives at the counting input of the lower counter 8, and the subtraction from the information previously set up in the counters 8-10 begins. Information from the outputs of counters 8-10 in the form

binary-decimal code enters the decoder 25. functioning only in the operating mode. The decoder 25 is controlled by a signal from the output of block 15. When determining the zero combination of all bits of counters 8-10, the signal from the output of the decoder 25 prohibits the passage of signals through the analyzer 27 and through the output driver 26 is sent to external devices for visual (audible) signaling end of frame in the camera or used to automatically control its shutdown

25

Claims (1)

Invention Formula A device for controlling the number of frames of a camera, containing a frame setter connected to an input driver, setter of the counter number, the output of which is connected to the input of the shift register, the output of which is connected to the first inputs of the correction enable valves, the outputs of which are connected to corresponding permissive inputs of the meters whose outputs are connected to the inputs of the decoders, the outputs of which are connected to the display unit, the mode selection unit, one of the inputs of which is connected with the output of an OR gate and an auxiliary pulse counter, characterized in that, in order to increase functionality by reducing information correction time and increase the reliability of operation by increasing the noise immunity of the device, a pulse generator is inserted into it, to the output of which a frequency divider is connected, a correction frequency multiplexer, signal switchboard, selectable counter selection valves, zero readout decoder with output driver, counter trigger signal generator and reliability analyzer the input signal that permits and zeroes the inputs of which are connected respectively to the output of the zero readings decoder and the input signal conditioner, the counting input is connected to one of the outputs of the frequency divider, and the output to the first input of the signal switch, the first inputs of other channels of which are connected to the outputs of older the counter inputs, and the second inputs are connected to the output of the correction frequency multiplexer, whose information inputs and control inputs are connected respectively to the outputs of the frequency divider and outputs spomogatelnogo counter, the count input of which is connected to an output of the frequency divider and the reset input is combined permissive frequency correction input of the multiplexer and is connected to the output of the start counter signal and to the second input of the mode selection unit whose output is connected to second inputs of Your account 17 I-vx count 17 Exit sietch 17 Output zero tilshsora20 0 five correction resolution gates, permissive input of the signal switch, control inputs of the display unit, zero readings and counters, the counting inputs of which are connected to the corresponding outputs of the signal switch, while the first inputs of the adjustable step selection gates are connected to one of the outputs of the frequency divider, the second inputs are connected with the outputs of the shift register and with the inputs of the logical element OR, and the outputs are connected to the control inputs of the decoders, the information inputs of the decoder n ulevy indications are connected to exits of counters