SU1668996A1 - Read-only memory - Google Patents

Abstract

The invention relates to computing and can be used in digital computing devices for calculating functions. The aim of the invention is to expand the field of application of the device by reading the values of not only direct, but also inverse functions. The device contains a decoder 1, a demultiplexer 2, a matrix of 3 storage elements, a multiplexer 4 and an encoder 5. The device allows reading the values of the forward and reverse monotonic functions. 2 tab., 4 Il.

Description

The invention relates to computing and can be used in digital computing devices for calculating functions.

The aim of the invention is to expand the field of application of the device by reading the values of not only the direct, but also the inverse function.

FIG. 1 shows a block diagram of the device;

in fig. 2 illustrates the construction of a functional matrix for realizing direct, 4X and inverse, 5Y functions; in fig. 3 - the same for forward YHogaX and inverse functions; in fig. 4-demultiplexer.

FIG. 2 and 3, each node of the matrix, marked with a dot, implements an electrical two-way communication between the vertical and horizontal lines, which are the input and output circuits of the matrix.

The device contains a decoder 1 whose inputs are operand inputs, a demultiplexer 2, an array of e-elements 3, a multiplexer 4, an encoder 5 whose outputs are the output of the device. The combined control inputs of the demultiplexer 2 and the multiplexer 4 are the input 6 of the device operation mode setting.

In a specific implementation of the device, a K155ID4 chip can be used as a decoder 1. Multiplexer 4 can be implemented on 555КП11 microcircuits. The demultiplexer 2 can be built on the elements of AND and HE- on the microcircuits 555LI1 and 555LN1, as shown in figure 4.

The encoder 5-can be built using the K555IV1 chip, which directly provides encoding of up to 8 signals at its inputs. In the case of a larger number of input signals, it is possible to encode them with the cascade connection of several such microcircuits. The matrix of the storage elements 3 can be implemented using the programmable logic matrix chip 556PT2. In addition, as the matrix 3, any LSI matrix structure with programmable (electrical or masked) connections can be used.

The device can read the values of monotonic functions (forward and reverse). The device capabilities are most fully manifested when reading the values of linear functions. The accuracy of the reproduction of the inverse linear function depends on its form. Let be ,

AY a (X + DH) -aX ADH.

Thus, if a 1, then the Y discretization of the discretization will be more DX. If a 1, then DU DU

Programming matrix 3 to implement the direct function, 4X table. 1, where the correspondence between the inputs and outputs of the matrix (the length of the input and output words) is indicated. Programming matrix 3 to implement the forward function Y log2X and the inverse function X antlog2 is explained in Table 2, where the operands X and Y are represented by binary words of 5 bits in length. 5 If we assume that using the matrix 3 functions, log2X is reproduced with a constant discretization step of the DF argument (equal to 1), then the inverse function will have a variable discretization step 0 of the remote control argument. This step depends on the size of the operands, 5 if 1 is U 2;

, 25 if 2 Y 3;

, 125 if 3 Y 4.

In general

DU Iog2 (X + DH) - logzX log X + VAX

Since Y 2, then 2y + 1

Control Iog2 02y

 1od2 (2y + 1) -Y.

Therefore, the inverse function is reproduced most accurately with large Y values.

The device can operate in two modes (depending on the control signal O or 1, which is fed to the input 6) and read the values of the direct or inverse function, respectively.

Let, for example, the control signal

0 is equal to O, thereby setting the readout value of the direct function, 4X. and Then, at the 5th output of the decoder 1, a single signal is transmitted that is the dem / liplexer 2

5 is transmitted to the 5th circuit of the first group of inputs of the matrix 3 (Figs. 1 and 2). The structure of matrix 3 is programmed so that the specified signal goes to circuit 8 of the first group of matrix outputs and then, through multiplex 4, to the eighth input of the encoder 5. As a result, the binary code of its input number appears on the outputs of the encoder 5, which has a single signal, te value, 00 (tab. 1).

5 When reading the value of the inverse function, 5Y the control signal at input 6 is 1. Let Y 11 11.10, then at the 14th output of the decoder 1 there appears a single signal switched by the demultiplexer 2 to the second group of matrix inputs

3. As a result of this, the ninth circuit of the second group of matrix outputs3 is excited. Then multiplexer 4 transmits a single signal to the ninth input of the encoder 5, and the output of its output is the value of the inverse function, 5 11 ,. The last value is rounded to the nearest number, fully recorded using four binary bits.

When reading the values of other direct and inverse functions (for example, Y log2X, in figs. 3 and 2), the device works in the same way.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A permanent storage device comprising a matrix of storage elements, a decoder, the inputs of which are informational inputs of the device, characterized in that, in order to extend the scope of application, by reading the values of both the forward and inverse functions, a demultiplexer, a multiplexer, and an encoder are entered into it, the outputs of which are the information outputs of the device, the outputs of the decoder are connected to the information inputs of the demultiplexer, the outputs of the first and second groups of which are connected respectively with information inputs of the first and second groups of the matrix of storage elements, the outputs of the first and second groups of which are connected respectively with the information inputs of the first and second groups of multiplexes Pa whose outputs are connected to the inputs of the encoder, the control inputs of the demultiplexer and multiplexer are combined and are the input of the device operation mode. Table 1  4 ° / 1№ &# 4 o / jf 3 + 5 6 8 9 10 14 12 "4 5  1 g.} “6 (/ 0 mini nil e / 6fi ffHci} iuitifttttiftSfif at one g t f t t / t te t / " / J ft if / 7 it ft to H yy s it ts 16 n g / g you n Fig 2 R Uprabs the washing P 9 and 4