SU1666977A1 - Voltage divider transfer gain meter - Google Patents

Abstract

The invention can be used for tolerance control of resistors during mass production. The purpose of the invention is to improve the measurement accuracy by eliminating the dependence of the final result on the magnitude of the conversion factor of the alternating voltage to constant. To do this, in the device, the signal input of the first voltage divider 2 is connected to the second input of the source 1 of the reference voltage, and its zero input is connected to the output of the second switch 14. In addition, the device contains the second voltage divider 3, the buffer amplifier 4, the first 5, the second 6 and third 7 pulse shapers, the frequency divider 8, which controls the first 13 and second 14 switches. The output of the second voltage divider 3 is through a series-connected AC voltage converter 9, analog-to-digital converter 10, as well as the first 11 and second 12 numeric registers connected to the inputs of the divider 15 codes, to the output of which the recording unit is connected. 1 il.

Description

ABOUT

ON O Yu

V4

VI

The invention relates to the field of digital measurement technology and can be used for tolerance control of resistors during mass production.

The aim of the invention is to improve the measurement accuracy by eliminating the dependence of the transmission coefficient on the magnitude of the conversion factor of the alternating voltage to constant voltage.

The drawing shows a diagram of a voltage divider's ratio meter.

The voltage meter of the voltage divider contains the source 1 of the reference voltage, the first 2 and second 3 voltage dividers, the buffer amplifier 4, the first B, the second 6 and the third 7 pulse shapers, the frequency divider 8, the AC voltage to constant converter 9, analog-to-digital converter (ADC) 10, the first 11 and second 12 numeric registers, the first 13 and second 14 switches, the divider 15 codes and the recording unit 16.

The first output of the source 1 of the reference voltage is connected to the common bus of the device, and the second output is connected to the second analog input of the switch 14 and the signal input of the voltage divider 2.

The zero input of the divider 2 voltage is connected to the output of the switch 14, and its output is connected to the input of the buffer amplifier 4. The output of the amplifier 4 through the first pulse shaper 5 is connected to the clock input of the frequency divider 8, the first analog input of the switch 13 and the signal input of the voltage divider 3 .

The zero input of the voltage divider 3 is connected to the output of the first switch 13, and the output is connected via serially connected inverter 9 AC to DC and the ADC 10 is connected to the information inputs of the numerical registers 11 and 12. The inverter first and second outputs of the frequency divider 8 are connected to the control the inputs of the switches 14 and 13 and the inputs of the second 6 and third 7 pulse shapers. The outputs of the formers 7 and 6 are connected to the clock inputs of the numeric registers 11 and 12, the outputs of which are connected to the divider 15 of the code, the output of which is connected to the input of the recording unit 16.

Second analog input of the switch

13 and the first analog input of the switch

14 are connected to the device common bus.

The reference voltage source 1 is designed to provide a reference alternating voltage. The shaper units 5-7 pulses serve to generate clock pulses. Frequency divider 8 is designed to issue control signals to switches 13 and 14 and drivers 6.7 pulses. He can

be made of a divider counter by 10, clocked by pulses from the output of the driver 5 pulses, and a trigger clocked by pulses from the output of this counter divider. Numeric registers 11 and

0 12 are used to store digital codes generated at the output of analog-digital converter 10. Dividers 2 and 3 are designed to reduce the voltage level from the outputs of voltage source 1 and

5 buffer amplifier 4. Buffer amplifier 4 is designed to coordinate the operation of the voltage divider 2 with other nodes of the device. It is an operational amplifier included in the circuit.

0 unit gain amplifier. The switch 14 serves to connect the zero input of the voltage divider 2 either to the output of the source 1 of the reference voltage or to the common bus. Switch 13

5 is designed to connect the zero input of the voltage divider 3 either to the common bus or to the output of the buffer amplifier 4. The converter 9 is designed to convert AC voltage

0 to a constant, and the A / D converter 10 to convert this constant voltage to a digital code. The code divider 15 serves to perform an arithmetic operation of dividing codes stored in numerical registers 11 and 12. The recording unit 16 serves to store and display the resulting code at the output of the code divider 15.

Gear ratio meter

0 voltage divider operates as follows.

In the initial state, the zero input of the voltage divider 2 through the switch 14 is connected to the common bus, and the zero input

5 voltage divider 3 through switch 13 - with the output of buffer amplifier 4.

In the first cycle, the alternating test voltage and, from the second output of the source 1 of the reference voltage, arrives at the signal input of the voltage divider 2, at the output of which the voltage Ugi is formed, equal to

c. -tsZBXI R2m

5 - Ul 7RTTTbT TR, lb (1)

where ZBxi is the input impedance of the buffer amplifier 4;

Ri, R2 is the resistance of the voltage divider resistors 2;

DM test voltage of reference voltage source 1

In the buffer amplifier 4, the voltage U1 is amplified by the value of the gain factor Ku 1. From the output of the amplifier 4, the voltage Uy goes to the signal input of the voltage divider 3, the output of which is the voltage

U24j l 2jЈi + R2 ..

9 yZBx2 (R + RJ) + Ri R2

 LU

Zoxl R2

ZnxTTRT + R2T + R R

, vZnx2 ()

X I4y, -G.

Znx2 (Rl + R2) + Rl R2

where RI RZ is the resistance of the voltage divider 3 resistors.

In converter 9, the voltage Ug2 is converted to a constant voltage Uni. equal to

Uni ug2 kp - uu zB7f (+ Rf iK ZBx2 (Ri + Rj) (

    7 "iNn i-J)

ZOX2 (Ri + R2 -t Ri R-

where Kp is the conversion factor of the alternating voltage into a constant converter 9;

Ku is the gain of the buffer amplifier 4.

In A / D converters 10, the voltage Uni is converted to a binary code NI, equivalent to the voltage Uni. and is fed to the information inputs of the numeric registers 11 and 12. The first clock cycle lasts 10 follow-up periods.

From the voltage Uy, at the output of the buffer amplifier 4. the forcing 5 pulses produces pulses with the following frequency Uu, which are then fed to the clock input of the frequency divider 8 The frequency divider 8 divides the frequency of the received pulses by 10, followed by the first and second) outputs of the divider 8, the frequencies are reversed.

In this case, the pulse shaper 6 generates a pulse, which records the NI code in the digital register 12 (at its clock input) coming from the ADC 10. Simultaneously from the second and first outputs of the frequency divider 8, the signals arrive at the control inputs of the switches 13 and 14 and switch them in the second clock state.

In the second cycle, the zero input of the divider 2 voltage through the switch 13 is connected to the second output of the source 1 of the reference voltage, and the zero bypass of the divider 3

five

ten

Voltage PG-RCZ ksmmuyuyur 14 with of 1 with a tire.

At the output of the voltage divider 2, a voltage U ji is formed. equal to

... (Ki - R2)

Uq, - U14 2- (Ж - + р R- -R- W

In the buffer amplifier 4, the voltage Ugi is amplified by the magnitude Ku 1, so that on the amplifier 4 the voltage Uy Ugi Ku occurs. The voltage Uy goes to the signal input of the voltage divider 3, the output of which voltage UgC is equal to

ZBXi (Ri + R2) x U ZexTTR 1 + R2T + R1 R2

CU

ZBX2 R21

(five)

ZBX2 (Rl -fR -f-Rl RJ In the inverter 9, the alternating voltage is converted into a constant voltage Ug2 into a constant voltage Un2 equal to

 ZexilRi + R2) „

Up2 - UU 2in1 p-- + Sh + R- R2

Znx2 R2

yZBx2 (Ri + R2)

Rlrj

CP,

(6)

In ADC 10, the voltage Un2 is converted to code N2. The second clock cycle also lasts for 10 follow-up periods Un, after which, similarly to the first clock cycle at the outputs of divider 8, the signal levels again reverse to opposite. The pulse shaper 7 generates a pulse, which writes the code N2 on the clock input in the numeric register 11. coming from the ADC 10. In this case, the switches 13 and 14 are switched to the first clock state.

The codes NI and N2 recorded in the first and second cycles in registers 12 and 11 are fed to the inputs of the divider 15 codes, where the arithmetic operation of calculating the resultant code N is performed using the formula

Ni / N2, (7)

where is ni. N2 - result codes 1 and 2 measurement cycles.

The N code is applied to the registering unit 16, where it is displayed in an operator-friendly manner (for example, in the form of digital information).

The resulting code N is equivalent to the ratio of the stresses Uni / Un and is equal to

U

1, ZBxi R

Kv

 Un2 ZBX (Ri + H :) + Ri

ZBx2 (R) + RJ) + Ri R2

ZBXi (Rl + R2) + RiR2 Uu ZBx1 (Ri + Rz) K7

ZBx2 (Ri + RJ) + Ri R.2 R2

ZBx2 R2

Ri + R2 K

Kn

Ri + R2

,eight

K1

(eight)

where K, K are the transfer coefficients of voltage dividers 2 and 3.

Expression (8) shows that the final resultant code is not affected by the input resistances ZBxi (buffer amplifier 4) and ZBx2 (converter 9 AC to DC), as well as the gain factor Qu (buffer amplifier 4) and AC voltage constant-voltage conversion (converter 9).

If the voltage divider 3 with the transmission coefficient K is taken as the reference, then the coefficient K of the voltage divider 2 under investigation can be determined from the expression

K N -K

i

Claims (1)

The invention The voltage divider of the voltage divider, containing the source of the reference voltage, the first output of which is connected to the common bus of the device, the second output - to the second analog input of the second switch, the first voltage divider, the output of which is connected with the input of the buffer amplifier, the output of which is connected to the first analog input of the first switch, the signal input of the second voltage divider and through the first pulse shaper to the clock input of the frequency divider, the zero input of the second voltage divider is connected to the output of the first switch, the output of the second voltage divider through serially connected AC / DC converter and analog-to-digital converter connected to the information inputs of the first and second numeric register , Vzaimoinversnye first and second outputs of the frequency divider are connected with the control inputs of the first and second switches and the inputs of the second and third pulse generators, whose outputs are connected to the clock inputs of the second and first numeric registers, the outputs of which are connected to the inputs of the code divider, the output of which is connected to the input of the recording unit, the second analog input the first switch and the first analog input of the second switch are connected to the common bus of the device, which is different from the fact that, in order to increase the measurement accuracy, the signal input of the first voltage divider is connected to the second output of the reference voltage source, and its zero input switch.