SU1665495A1 - Device for comparing closely spaced frequencies - Google Patents

Abstract

The invention relates to a pulse technique and can be used in high-precision measuring systems. The purpose of the invention is to improve the accuracy of the comparison by obtaining the digital value of the frequency difference. To achieve the goal, the device containing the triggers 1-5, the element OR 10, the reversible counter 12 pulses, the elements AND 6-9, the element OR 11 and the new connections are entered. The device provides a summation of the number of clock pulses from the bus 15 in the reversible counter 12 over the period of pulses on the input bus 13 and the subsequent subtraction of the number of clock pulses over the period of the pulses on the bus 14. At the same time, a code proportional to the difference of the periods of the pulses on the input buses is formed on the output bus 17 13 and 14. Since one of the input frequencies is fixed, this code gives information about the difference in input frequencies. The presence or absence of an overflow pulse on bus 18 indicates the difference between the compared frequencies. 2 Il.

Description

The invention relates to a pulse technique and can be used in high-precision measuring systems.

The purpose of the invention is to increase the accuracy of comparison by obtaining a digital value of the frequency difference.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 - timing diagrams characterizing the operation of the device.

The device contains first to fifth triggers 1-5, first to fourth elements AND 6-9, first 10 and second 11 OR elements, a reversible counter of 12 pulses, the first 13 and second 14 input buses, bus 15 clock pulses, bus 16 start, first 17 and second 18 output tires.

The bus 16 is connected to the S-input of the first trigger 1, R-inputs of the second 2, third 3, fourth 4 and fifth 5 triggers and a reverse counter 12. The outputs of the first 1 and second 2 triggers are connected to the first inputs of the first 6 and second 7 elements And, the second inputs of which are connected to the first 13 and second 14 input buses, and the outputs - with the counting inputs of the third 3 and fifth 5 triggers. The output of the third trigger 3 is connected to the R-input of the first trigger 1, the S-input of the second trigger 2 and the first input of the third element And 8, the output of which is connected to the first input of the first element OR 10, the second input of which is connected to the direct output of the fifth trigger 5, S '-input of the fourth trigger 4 and the first input of the fourth element And 9, the second input of which is connected to the second input of the third element And 8 and bus 15, and the output is connected to the first input of the second element OR 11, the second input of which is connected to the inverse output of the fifth trigger 5 Third WTO entrance The first AND 7 element is connected to the inverse output of the fourth trigger 4, and the outputs of the first 10th second 11 OR elements are connected to the summing and subtracting inputs of the reverse counter 12, the overflow output and output of which are connected to the first 17 and second 18 output buses.

The device operates as follows.

Signals F ^! i = F-> ± AF and F ^ enter the input buses 13 and 14 (Fig. 2, a and b). With the arrival of the trigger pulse * '(FIG. 2, c), the device is put into operation, the mode of determining the magnitude and sign of the difference of two frequencies. Triggers 2-5 and the reverse counter 12 are reset by this pulse to the zero state, and trigger 1 is set to G. A high level signal from its direct output goes to element And 6 (Fig. 2, e). With the arrival of the first pulse of frequency F? element And 6 opens by switching trigger 3 (Fig. 2, g and h). A high level from the direct output of trigger 3 opens the And 8 element, allowing the passage of clock pulses of the signal to the summing input of the reversing counter 12 (Fig. 2, p). To ensure the counting mode, a high signal level must be applied to the subtracting input of the reversing counter 12. This is achieved by feeding from the inverse output of the trigger 5 (Fig. 2, k) a high level through the element OR 11 (Fig. 2, c).

With the arrival of the second pulse of signal Fi, trigger 3 is transferred to state 0, excluding the further passage of clock pulses through element And 8 to the summing input of the reversible counter 12 ..

The trailing edge of trigger 3 (Fig. 3, h) trigger · 2 switches to state 1 (Fig. 2, i), and with the arrival of a pulse with frequency F2 ^{1, the} signal from the output of element And 7 (Fig. 2, k) is fed to T -input of trigger 5, switching it to ”1 (Fig. 2, m) and thereby opening the And 9 element. Until the signal F2 * appears, the reverse counter 12 does not subtract, since there is a signal at the summing input (Fig. 2, d) low level taken from the direct output of trigger 5. With the arrival of the signal F2 ¹ , “1 appears on the direct output of trigger 5, the counter 12 is counted down. With the arrival of the second pulse F2 ¹ trigger 5 is reset to 0. According to this differential trigger 4 is converted to 1, and at its inverse output (Fig. 2, k) there will be a low level prohibiting the passage of signal F2 'through the And 7. At the summing input of the reverse counter 12 at this moment, a low signal level will come in, thereby prohibiting the account from the subtracting input.

Thus, a code proportional to the difference between the periods of the signals F1 ¹ and F2 ^J is generated in the reverse counter 12. Since one of these signals has a fixed frequency, the code on the output bus 17 gives accurate information about the frequency difference F? and F2 ¹ 'When overflowing the reverse counter 12 in the subtraction mode, an impulse appears on the output bus 18, which can be fixed. The presence or absence of this pulse gives information about the sign of the difference between the two frequencies.

Claims (1)

Claim A device for comparing two close frequencies, containing from the first to fifth triggers, a clock pulse bus, a reversible pulse counter, the output of which is connected to the first output bus, the first OR element, the first and second input buses, the second output bus, which differs from I mean that, in order to increase the accuracy of comparison by obtaining a digital value of the frequency difference, 5 elements And, a second element OR and a trigger bus connected to the S-input of the first trigger and R-inputs of the second, third are introduced into it 5 fourth and fifth triggers and a reversible counter of 10 pulses, the outputs of the first and second triggers being connected to the first inputs of the first and second elements AND, respectively, the second inputs of which are connected to the first and second input buses, respectively, and the outputs to the counting inputs of the third and fifth respectively, the output of the third trigger is connected to the R input of the first trigger, the S-input of the second trigger and the first input of the third AND element, the output of which is connected to the first input of the first OR element, the second input of which is connected nen with the direct output of the fifth trigger, the S-input of the fourth trigger and the first input of the fourth AND element, the second input of which is connected to the second input of the third And element and the clock bus, and the output is connected to the first input of the second OR element, the second input of which is connected to the inverse the output of the fifth trigger, while the third input of the second AND element is connected to the inverse output of the fourth trigger, and the outputs of the first and second OR elements are connected respectively to the summing and subtracting inputs of the reversible pulse counter s whose overflow output is connected to the second output bus.